ASIC Design Verification Engineer

Advanced Micro Devices; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Advanced Micro Devices is seeking a Staff Silicon Design Verification Engineer to lead verification of high-speed Crypto, NoC, and memory controller IPs at IP and SoC levels.

The ideal candidate will guide verification strategy, craft testbenches with UVM/SystemVerilog, and mentor teams to deliver high-quality silicon on schedule.

Qualifications

• Requires BS with 8+ years or MS with 6+ years or PhD with 3+ years in Electrical Engineering, Computer Engineering or Computer Science.
• Proven leadership in verification strategies for IP or SoC designs.
• Experience with UVM and SystemVerilog testbenches; strong verification methodology knowledge.

Responsibilities

• Lead verification of high-speed Crypto, NoC, and DRAM memory controllers to ensure first-pass silicon quality.
• Architect, develop, and reuse simulation and formal verification environments at IP and SoC levels.
• Lead and mentor verification teams, plan execution, tracking, and program delivery.
• Develop comprehensive verification plans with testbenches and tests; drive verification closure.

Skills

Technical leadership

Verification leadership

UVM

SystemVerilog

Education

BS in EE/CE/CS

MS in EE/CE/CS

PhD in EE/CE/CS

Tools

Synopsys VCS

Cadence Xcelium

VC Formal

JasperGold

Questa Formal

Mentor Questa Formal

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

ASIC DESIGN VERIFICATION ENGINEER

THE ROLE:

Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.

THE PERSON:

The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality.

Key Responsibilities:

• Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance.


• Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.


• Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.


• Develop and execute comprehensive verification plans, including testbenches and test cases.


• Collaborate with design, architecture, and software teams to define and implement verification strategies.


• Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.


• Mentor and guide junior engineers, fostering a collaborative and innovative team environment.

PREFERRED EXPERIENCE:

• Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.


• Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS orCadence Xcelium.


• Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus.


• Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management.


• Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus.


• Experience with gate-level simulation, power-aware verification is a plus.


• Experience with silicon debug at the tester and board level, is a plus.

ACADEMIC CREDENTIALS:

• Require BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering or Computer Science.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.