Analog Design Flow and Infrastructure Design Automation Manager

Intel; Bengaluru; Hybrid; INR 4,000,000 - 7,000,000; Full time

Job summary

Intel in Bengaluru, India, seeks an experienced Analog Design and Infrastructure DA Manager to lead analog/mixed-signal design environments, CAD infrastructure, and tapeout governance. You will own EDA tool ecosystems, PDK integration, and compute infrastructure to ensure reproducibility and audit readiness across silicon programs.

The ideal candidate combines deep analog flow expertise with infrastructure leadership, data governance, and disciplined configuration management.

Qualifications

• 10+ years of experience in analog/mixed-signal design or CAD support.
• 5+ years of leadership experience.
• Hands-on with Virtuoso and p-cell development.
• Deep understanding of analog layout, verification, PDK integration, and tapeout processes.
• Experience with design data governance and tapeout manifest control.
• Strong Linux administration and scripting (Python, Tcl, Shell, SKILL).
• Experience with compute grid management, storage architecture, and license management.
• Expertise in version control and configuration management systems.

Responsibilities

• Own analog design environment and flow management including LVS, DRC, and automation.
• Oversee DA infrastructure, compute farms, storage, and license servers.
• Manage tapeout manifests, PDK/tool versions, and environment reproducibility.
• Lead and mentor DA and infrastructure engineers; drive governance and cross-functional collaboration.

Skills

Analog/mixed-signal design

Leadership

Python scripting

Shell scripting

Version control

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Virtuoso

HSPICE

LVS/DRC

Git

Cliosoft

SVN

Perforce

Job description

Job Details

We are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices.

Key Responsibilities

• 1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness.
• 2. Infrastructure and Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies.
• 3. Design Data, Manifest and Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed storage systems optimized for EDA workloads. Manifest and Tapeout Release Management Own creation and governance of tapeout manifests including: PDK Versions, Tool Versions, Extraction/Verification Decks, Simulation Models, Signoff Configurations Establish reproducible environment release frameworks for analog programs. Implement controlled qualification flows for tool/PDK upgrades prior to production rollout. Maintain environment snapshots to ensure reproducibility and post-silicon traceability. Support formal tapeout readiness and design signoff reviews. Version Control and Configuration Management Deploy and manage version control systems (Git, Cliosoft, SVN, Perforce,) for: CAD scripts and automation, Methodology flows, PDK overlays, Verification decks Define branching, tagging, and release strategies for multi-project and multi-node environments. Implement dependency tracking across tools, PDKs, IP, and infrastructure. Apply infrastructure-as-code principles where applicable. Automation and Traceability Develop automated environment capture tools to log tool versions, library states, and system configurations. Enable reproducible simulations and environment packaging. Create dashboards and reporting metrics for design data health and DA service KPIs.
• 4. Leadership and Cross-Functional Collaboration Lead and mentor DA and infrastructure engineers. Serve as the primary interface between analog design, digital CAD, IT, and EDA vendors. Drive tool evaluations, upgrades, and vendor negotiations. Develop internal documentation, training programs, and best practices. Establish measurable service-level KPIs and continuously improve DA operations.

Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in analog/mixed-signal design or CAD support. 5+ years of leadership experience. Strong hands-on experience with analog design platforms such as Virtuoso and p-cell development. Custom Compiler. Deep understanding of analog layout, verification flows, PDK integration, and tapeout processes. Proven experience managing design data governance and tapeout manifest control. Strong Linux system administration and scripting skills (Python, Tcl, Shell, SKILL). Experience with compute grid management, storage architecture, and license management. Expertise in version control and configuration management systems.

Preferred Qualifications Experience with advanced nodes (FinFET, GAA). Knowledge of CI/CD practices applied to EDA environments. Experience supporting geographically distributed design teams

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.