Analog Design Engineer - PMIC - Staff/ Senior Staff

TylSemi, Inc.; Bengaluru; Remote; INR 4,000,000 - 7,500,000; Full time

Job summary

TYLsemi, Inc. in Bengaluru seeks a Staff/Senior Staff Analog Design Engineer to design high-performance analog and mixed-signal circuits for robust silicon.

The role spans 5–30 years of experience, translating system requirements into silicon-ready designs and validating across corners with layout, verification, test, and product teams to drive first-time-right outcomes. You will lead PMIC/IVR/DC-DC design, model control loops, and collaborate with packaging teams for co-optimization.

Qualifications

• Experience in analog/mixed-signal IC design for PMICs and power delivery.
• Track record shipping silicon with high-current, high-efficiency regulators.
• Experience with modeling and verification across PVT.

Responsibilities

• Design PMIC power stages, regulators, and sensing circuits.
• Model control loops and DVFS for robust performance.
• Collaborate with packaging and integration teams for co-design.

Skills

Analog/mixed-signal design

PMIC/DC-DC converters

High-current/high-efficiency design

Power management experience

Strong collaboration & comms

Education

BS/MS/PhD in Electrical Engineering (Analog & Mixed-Signal)

Tools

Cadence Virtuoso

Spectre

Clarity/EMX

MATLAB/Simulink

2.5D/3D packaging flows

Job description

About this position

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn’t fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don’t care about titles or politics. We care about results.

The Ask

If you’re reading this, you’re probably comfortable. You have a good job at a stable company with all the benefits.

We’re asking you to walk away from that and bet on us.

Here’s why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we’re building.
• The team has done this before. We’ve built and exited semiconductor companies at scale. This isn’t our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You’re not optimizing someone’s ad click-through rate. You’re building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you’re the kind of person who wants to take the shot, we’d love to talk.

READY TO JOIN?

Role Overview

As a Staff /Senior Staff Analog Design Engineer at TYLsemi, you will design and deliver high-performance analog and mixed-signal circuits that enable robust, manufacturable silicon. This role spans a wide experience range (5-30 years) and is ideal for engineers who combine strong fundamentals with practical execution—translating system requirements into silicon-ready designs, validating performance across corners, and partnering closely with layout, verification, test, and product teams to drive first-time-right outcomes.

WhatYou’llDo

• Design of Voltage Regulators including high-efficiency power stages, error amplifiers, current sensing, adaptive load-line circuits, fast transient compensation, protection and telemetry.
• Modeling of mixed-signal subsystems including Regulator control loops, Power delivery network, DVFS subsystems etc. to guide architecture and design trade-offs
• Lead the collaboration with SIPI/PI, packaging teams to co-optimize VR and power delivery.

WhatWe’reLooking For

• 7 to 14 years of hands-on analog/mixed-signal IC design experience with a strong focus on high-current, high-efficiency Power management (PMIC / IVR / DC-DC converters).
• Deep expertise in different voltage regulator topologies including control loops delivering large current at high switching frequencies.
• Hands-on experience in magnetics integration for high-density IVR — including inductor modeling, coupling effects, EMI/thermal co-optimization, and 3DIC package integration.
• Proficiency with industry-standard design and modelling tools including Cadence Virtuoso, Spectre, Clarity/EMX, MATLAB/Simulink.
• Experience in 2.5D, packaging flows and co-design with SIPI/PDN teams.
• Team player with excellent communication skills
• BS / MS / PhD in Electrical Engineering (Analog & Mixed-Signal focus)

Nice to Have

• Experience with state-of-the-art AI/HPC power delivery .
• Experience in designing power management switching regulators, including Buck, Boost, Buck-Boost, LDO, and other PMIC building blocks.
• Strong background in power management circuits such as LDOs, bandgap references, voltage/current references, protection circuits, start-up circuits, transient response optimization, and related analog power management functions.
• Familiarity with advanced packaging flow and thermal/PI co-optimization

Success in This Role Looks Like

• Analog blocks meet spec with margin across PVT, mismatch, and post-layout effects
• Design reviews are crisp: requirements, tradeoffs, and risks are clearly articulated and managed
• Silicon bring-up converges quickly through strong correlation, structured debug, and decisive fixes
• Cross-functional partners (layout, verification, test, validation) can execute efficiently with clear interfaces and documentation
• Reusable design collateral and improved methodology reduce cycle time and increase first-pass success