Analog Circuit Design Engineer (3–15 Years)

SILCOSYS Solutions Pvt. Ltd.; Bengaluru; Sur place; INR 1 400 000 - 2 200 000; Plein temps

Résumé du poste

SILCOSYS Solutions Private Limited seeks experienced Analog Circuit Design Engineers for transistor-level analog design, simulation, verification, and optimization. Projects include voltage/clock monitoring, capless LDOs, buffer amplifiers, and high-voltage I/O with preference for capless LDOs and FuSa-related work.

You will own blocks, simulate, troubleshoot, and collaborate with cross-functional teams. Key responsibilities cover design, analysis, and extensive simulations

Qualifications

• Hands-on transistor-level analog circuit design, simulation and verification.
• Experience with voltage/clock monitoring, LDOs, buffer amplifiers, and high-voltage I/O is a plus.
• Capable of independent block ownership and cross-functional collaboration.
• Perform DC/AC/transient, PVT corner, and Monte Carlo simulations.
• Debug circuit issues and contribute to design reviews.

Responsabilités

• Design, develop, simulate, and verify analog circuits at transistor level.
• Perform circuit analysis, transistor sizing, biasing, and optimization.
• Run DC, AC, transient, stability, PVT, and Monte Carlo simulations.
• Optimize for power, accuracy, stability, noise, area, and reliability.
• Debug issues and support design reviews and documentation.
• Collaborate with layout and verification to address parasitics and post-layout performance.
• Support porting, migration, and validation across nodes.

Connaissances

CMOS analog design

Transistor-level circuit design

Analog simulation

Cadence Virtuoso

Cadence Spectre

DC/AC/Transient/PVT/Monte Carlo sims

Parasitic analysis

Cross-functional collaboration

Formation

B.E./B.Tech in Electronics and Communication Engineering, Electrical Engineering or related

Outils

Cadence Virtuoso

Cadence Spectre

Description du poste

Silcosys Solutions Private Limited is looking for experienced Analog Circuit Design Engineers with strong hands-on expertise in transistor-level analog circuit design, simulation, verification, and optimization.

The engineers will work on voltage and clock monitoring circuits, capless LDOs, buffer amplifiers, conventional LDOs, power switches, and high-voltage I/O circuits. Candidates with specialized experience in comparator design, functional safety (FuSa), analog built-in self-test (BIST), capless LDO design, chopping amplifiers, and high-voltage I/O design will be preferred.

We are looking for candidates who can independently own circuit blocks, perform detailed circuit simulations, troubleshoot design issues, and collaborate with cross-functional design teams.

Key Responsibilities

• Design, develop, simulate, and verify analog circuits at the transistor level.
• Perform circuit analysis, transistor sizing, biasing, and performance optimization.
• Conduct DC, AC, transient, stability, PVT corner, and Monte Carlo simulations, as applicable.
• Optimize circuit performance for power, accuracy, stability, noise, area, and reliability.
• Debug circuit-level issues and support design reviews and technical documentation.
• Collaborate with layout and verification teams to address parasitic effects and post-layout performance.
• Support design porting, circuit migration, and validation across technologies or process nodes.
• Work on one or more of the following specialized circuit design requirements.

Project-Specific Requirements

AC1 – Voltage and Clocking Monitor Circuits (3–15 Years)

Preferred expertise:Comparator design, voltage monitoring, analog BIST, and functional safety.

Responsibilities:

• Design voltage and clocking monitor circuits.
• Develop comparator-based undervoltage and overvoltage detection circuits.
• Design voltage window monitoring circuits with appropriate thresholds, accuracy, and response characteristics.
• Support analog built-in self-test (BIST) implementation and verification.
• Contribute to functional safety (FuSa)-related circuit requirements and diagnostic coverage, where applicable.
• Perform PVT, offset, noise, and transient simulations to validate circuit performance.

AC2 – Capless LDO Design (3–15 Years)

Preferred expertise:Capless Low-Dropout Regulator (LDO) design.

Responsibilities:

• Design and optimize capless LDOs for 1.2 V and 3.3 V applications.
• Develop regulator circuits that maintain stability without an external output capacitor, subject to design specifications.
• Analyze loop stability, load and line regulation, dropout voltage, transient response, PSRR, and quiescent current.
• Perform compensation design and stability analysis across PVT corners and varying load conditions.
• Conduct circuit-level simulations and troubleshoot stability and performance issues.

AC3 – Buffer Amplifier and Power Switch Porting (3–15 Years)

Preferred expertise:Buffer amplifier design and chopping amplifiers.

Responsibilities:

• Design a buffer amplifier operating between the3.5 V Zener reference and the 1.2 V VrefBuffer stage.
• Evaluate and implement suitable amplifier architectures to meet reference accuracy, noise, offset, and load-driving requirements.
• Apply chopping amplifier techniques, where appropriate, to reduce offset and low-frequency noise.
• Perform circuit simulations to validate accuracy, stability, settling time, and other specified performance parameters.
• Handle the porting of power switches to the target technology or design platform and validate their functionality.

AC4 – LDO with External Capacitor and High-Voltage I/O (3–15 Years)

Preferred expertise:LDO design and high-voltage I/O circuits.

Responsibilities:

• Design and verify an LDO with an external output capacitor.
• Analyze loop stability, compensation requirements, load regulation, line regulation, PSRR, dropout voltage, and transient response.
• Validate regulator performance for the specified external capacitor and load conditions.
• Design high-voltage I/O circuits forPGPIO and WAKE pins.
• Address voltage tolerance, device reliability, leakage, protection, and interface requirements according to the target process and specifications.
• Perform circuit simulations and support debugging and verification of the high-voltage I/O designs.

Required Technical Skills

• Strong fundamentals in CMOS analog circuit design and semiconductor device operation.
• Hands-on experience in transistor-level circuit design and analog simulation.
• Proficiency with Cadence Virtuoso and Spectre, or equivalent analog design and simulation tools.
• Experience with DC operating-point, AC, transient, PVT corner, and Monte Carlo simulations.
• Understanding of feedback systems, stability, compensation, noise, offset, and parasitic effects.
• Ability to analyze simulation results, resolve circuit issues, and optimize designs against specifications.
• Familiarity with design porting, process design kits (PDKs), and technology-specific constraints.
• Good problem-solving, communication, and cross-functional collaboration skills.

Preferred Qualifications

Experience in one or more of the following areas will be advantageous:

• Comparator design and voltage window monitors.
• Undervoltage and overvoltage detection circuits.
• Analog BIST and functional safety (FuSa).
• Capless LDO design for multiple output voltages.
• External-capacitor LDO design and loop compensation.
• Buffer amplifiers and chopping amplifier architectures.
• Power switch porting and validation.
• High-voltage I/O design, including PGPIO and WAKE interfaces.

Educational Qualifications

B.E./B.Tech or M.E./M.Tech in Electronics and Communication Engineering, Electrical Engineering, VLSI Design, or a related discipline.

Experience Requirements

3–6 Years

• Hands-on circuit design, simulation, debugging, and verification experience in a relevant analog design area.

7–10 Years

• Independent ownership of analog blocks, optimization, and resolution of complex circuit design issues.

11–15 Years

• Advanced circuit design expertise, technical reviews, design ownership, and mentoring, as applicable to the project.

Candidates are not expected to have expertise in every circuit listed above. Strong experience in the specific design area relevant to the assigned project is essential.

Job Location and Availability

• Experience:3–15 years
• Notice Period:Immediate to 30 days
• Joining Preference:Candidates available to join immediately or within 30 days.