Analog Circuit Design Engineer

Intel; Karnataka; Hybrid; INR 1,800,000 - 3,400,000; Full time

Job summary

Intel in Bengaluru seeks an experienced Analog Designer to lead design and development of advanced analog and mixed-signal circuits enabling high-speed chip-to-chip connectivity. You will own critical IP blocks from concept through silicon validation, mentoring junior engineers and collaborating across architecture, digital design, and validation teams.

The role requires strong transistor-level design, background in high-speed IO architectures, and hands-on experience with Cadence Virtuoso and

Qualifications

• Bachelor's or master's degree in electrical/electronics engineering or related discipline.
• 5–9 years of analog/mixed-signal IC design experience.
• Strong CMOS analog fundamentals and high-speed circuit design experience.

Responsibilities

• Lead design, analysis, and optimization of analog/mixed-signal circuits for high-speed IO interfaces.
• Architect and implement TX/RX circuits, SerDes building blocks, PLLs/DLLs/CDRs, and clocking circuits.
• Collaborate with physical design, layout reviews, and post-layout optimization.
• Support silicon bring-up, characterization, and validation against simulations.

Skills

Analog design

High-speed IO

Mentoring

Signal integrity

Scripting (Python/TCL)

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Job description

Job Details

Intel is looking for an experienced Analog Designer to join the IO Design Team in Bengaluru. In this role, you will be responsible for leading the design and development of advanced analog and mixed-signal circuits that enable high-speed chip-to-chip, package-to-package, and system-level connectivity for Intel's next-generation products.

The ideal candidate will have a strong background in transistor-level circuit design, high-speed IO architectures, and silicon debug. This position requires technical leadership, cross-functional collaboration, and ownership of critical IP blocks from concept through silicon validation.

Key Responsibilities

• Lead the design, analysis, and optimization of analog and mixed-signal circuits for high-speed IO interfaces.
• Develop and drive architecture and circuit implementation for:
  • High-speed TX and RX circuits
  • Serializer/Deserializer (SerDes) building blocks
  • PLLs, DLLs, CDRs, and clocking circuits
  • Equalization and signal conditioning circuits
  • Bandgap references, bias generation, and LDOs
  • ESD protection and IO pad circuitry
• Perform detailed transistor-level design, simulation, and verification across multiple PVT corners.
• Drive design closure for performance metrics including bandwidth, jitter, noise, power, area, yield, and reliability.
• Collaborate closely with physical design teams on layout reviews and post-lay out optimization.
• Support silicon bring-up, characterization, root-cause analysis, and correlation between simulation and silicon measurements.
• Work with architecture, digital design, signal integrity, package, product engineering, and validation teams to ensure successful product execution.
• Mentor junior engineers and contribute to team-wide design methodologies and best practices.
• Drive technical reviews and provide leadership in solving complex design challenges.

Qualifications

• Bachelor's or master's degree in electrical engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.
• 5 to 9 years of industry experience in analog/mixed-signal IC design.
• Strong expertise in CMOS analog circuit design fundamentals.
• Proven experience designing high-speed analog circuits in advanced technology nodes.
• Hands-on experience with one or more of the following: SerDes architectures, High-speed IO interfaces, PLL/DLL/CDR circuits, TX/RX analog front-end circuits, Clock distribution networks, Reference and bias circuits, LDOs and power management circuits.
• Deep understanding of circuit noise, mismatch, jitter, stability, and reliability considerations.
• Strong experience with Cadence Virtuoso, Spectre, and industry-standard analog verification flows.
• Expertise in: Corner analysis, Monte Carlo simulations, Statistical design methodologies, post-layout verification and extraction analysis, Strong debugging and analytical problem-solving skills.
• Experience with industry-standard high-speed interfaces such as: PCI Express (PCIe), DDR Memory Interfaces, USB, Ethernet, MIPI, DP, eDP, HDMI, UCIe.
• Experience in advanced process technologies such as FinFET and Gate-All- Around (GAA) nodes.
• Knowledge of signal integrity, channel modelling, and equalization techniques.
• Experience in silicon validation and lab characterization.
• Familiarity with reliability signoff, ESD verification, and EM/IR analysis.
• Scripting experience using Python, Perl, TCL, or SKILL for design automation and productivity enhancement.

Key Competencies

• Technical leadership in analog and mixed-signal design.
• Strong communication and stakeholder management skills.
• Ability to work effectively in global, cross-functional environments.
• Structured problem-solving and decision-making capabilities.
• Passion for innovation and continuous improvement.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Position of Trust

N/A

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during your hiring process, please report this immediately to your recruiter.