Analog circuit design engineer

Weekday AI; Bengaluru; On-site; INR 1,500,000 - 3,500,000; Full time

Job summary

Weekday AI is seeking an Analog Circuit Design Engineer in Bengaluru with 3+ years of hands-on experience in analog and mixed-signal IC design. The role emphasizes PLL and SerDes circuit development, FinFET technology considerations, and rigorous LVS/DRC verifications across PVT conditions.

The position requires collaboration with cross-functional teams, post-layout validation, and a focus on high-performance, power-efficient circuits for advanced semiconductor applications.

Qualifications

• Experience in analog/mixed-signal integrated circuit design.
• Hands-on PLL design and/or SerDes development.
• Familiarity with LVS/DRC and physical verification workflows.

Responsibilities

• Design, analyse, and optimise analog and mixed-signal circuits.
• Develop and verify PLL circuits for clocking performance and jitter.
• Contribute to SerDes circuit design for high-speed data transmission.
• Perform transistor-level simulations across PVT variations.
• Collaborate with layout engineers for accurate implementation.
• Perform LVS and DRC checks and resolve schematic-layout mismatches.
• Support post-layout simulation and parasitic analysis.
• Document simulations and verification results.

Skills

Analog/mixed-signal design

PLL design

SerDes design

FinFET technologies

PVT analysis

LVS knowledge

DRC knowledge

Circuit verification

High-speed circuit design

Education

Bachelor's or Master's in Electrical/Electronics/VLSI

Tools

Cadence Virtuoso

Spectre

HSPICE

Job description

This role is for one of the Weekday's clients

Salary range: Rs 1500000 - Rs 3500000 (ie INR 15-35 LPA)

Experience: 3+ yrs

Location: Bengaluru, Karnataka, India, Hyderabad, Telangana, India

We are looking for a skilledAnalog Circuit Design Engineerwith hands-on experience in analog and mixed-signal integrated circuit design. The ideal candidate will have strong technical expertise inPhase-Locked Loops (PLL), SerDes, FinFET technologies, and physical verification processes, including Layout Versus Schematic (LVS) and Design Rule Checks (DRC).

This role involves designing, analysing, verifying, and optimising high-performance circuits for advanced semiconductor applications. You will collaborate with cross-functional engineering teams to develop robust, power-efficient, and high-speed circuit solutions while ensuring design accuracy, reliability, and compliance with technology-specific requirements.

Key Responsibilities

• Design, analyse, and optimise analog and mixed-signal circuits for advanced semiconductor applications.
• Develop and verifyPLL circuits, focusing on frequency generation, clocking performance, stability, and jitter characteristics.
• Contribute toSerDes circuit designfor high-speed data transmission and signal integrity.
• Perform transistor-level circuit simulations and analyse performance across process, voltage, and temperature (PVT) variations.
• Work withFinFET technologyand understand its impact on circuit behaviour, power consumption, and performance.
• Collaborate with layout engineers to ensure accurate implementation of circuit designs.
• Perform and debugLVS and DRC checks, resolving schematic-to-layout mismatches and design rule violations.
• Support post-layout simulation, parasitic analysis, and circuit performance optimisation.
• Investigate circuit functionality, timing, noise, power, and reliability issues.
• Participate in design reviews and collaborate with cross-functional engineering teams.
• Maintain design documentation, simulation results, verification reports, and technical specifications.
• Follow established semiconductor design methodologies, verification standards, and quality practices.

What Makes You a Great Fit

• 3+ years of experiencein analog or mixed-signal integrated circuit design.
• Strong understanding of analog circuit fundamentals, transistor-level design, and semiconductor device characteristics.
• Hands-on experience withPLL design and/or SerDes circuit development.
• Knowledge ofFinFET process technologiesand advanced-node semiconductor design considerations.
• Practical experience withLVS, DRC, and physical verification workflows.
• Familiarity with circuit simulation tools such as Cadence Virtuoso, Spectre, or HSPICE.
• Understanding of PVT analysis, post-layout simulation, parasitic effects, and circuit optimisation.
• Strong debugging, analytical, and problem-solving skills.
• Ability to collaborate effectively with circuit design, layout, and verification teams.
• A Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline is preferred.