Analog and Mixed Signal Layout Engineer

Lumilens Inc.; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

Lumilens Inc. is seeking an experienced Analog and Mixed Signal Layout Engineer in Bengaluru.

You will design, implement, and optimize complex analog, mixed-signal, and RF layouts for high-performance connectivity IPs, collaborating with circuit designers from floorplanning to tapeout. The role emphasizes ownership of signoff, RC extraction, and DFM, with exposure to silicon photonics and advanced CMOS technologies.

Qualifications

• BE/B.Tech or MS/M.Tech in Electrical/Electronics with 5–10 years in analog/mixed-signal layout.
• Hands-on experience with layouts for SerDes, data converters, or RF blocks.
• Proven full-custom layout and signoff experience (RC extraction, DRC, LVS, ERC, DFM, EMIR).
• Familiarity with silicon photonics or high-bandwidth connectivity is a plus.

Responsibilities

• Develop high-speed connectivity IPs using advanced semiconductor process technologies.
• Design and implement complex analog, mixed-signal, and RF layouts for IPs, including floorplanning and routing.
• Work with circuit designers to translate schematics into physical implementations from floorplanning to tapeout.
• Own physical verification and signoff closure (DRC, LVS, ERC, DFM, EMIR).
• Optimize layouts using extraction results to meet performance and reliability targets.
• Contribute to layout reviews and drive best practices.
• Improve layout productivity and quality through automation, scripting, and AI-assisted workflows.
• Develop high-performance connectivity IPs used in AI, networking, and compute systems.

Skills

Analog layout

Mixed-signal layout

Cadence Virtuoso

Scripting/Automation

RF layout

Signoff expertise

Education

BE/B.Tech or MS/M.Tech in Electrical/Electronics

Tools

Cadence Virtuoso

Other EDA tools

Job description

Analog and Mixed Signal Layout Engineer

About Lumilens

At Lumilens, we’re building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. Our technology enables faster, cooler, and more efficient computing through cutting-edge optical solutions and high-performance connectivity IPs. If you're driven by innovation and eager to shape the future of AI infrastructure, we invite you to join our world-class engineering team.

What You Can Expect

• Play a key role in developing high-speed connectivity IPs using advanced semiconductor process technologies.

• Design and implement complex analog, mixed-signal, and RF layouts for high-performance connectivity IPs, including floorplanning, device placement, and routing.

• Work closely with circuit designers to translate schematics into robust physical implementations from floorplanning through tapeout.

• Own physical verification and signoff closure including DRC, LVS, ERC, antenna, DFM, and EMIR.

• Optimize layouts using extraction results to meet performance, matching, noise, and reliability targets.

• Contribute to layout reviews and help drive effective layout methodologies and best practices.

• Improve layout productivity and quality through automation, scripting, and AI-assisted workflows.

• Develop high-performance connectivity IPs used in AI, networking, and next-generation compute systems.

What We’re Looking For

• BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or a related field with 5-10 years of experience in analog, mixed-signal, RF, or custom layout development.

• Hands-on experience with layouts for SerDes, data converters, clocking circuits, power management, transceiver building blocks, or related connectivity IPs.

• Proven experience in full-custom layout and signoff including RC extraction, DRC, LVS, ERC, DFM, and EMIR.

• Exposure to silicon photonics, co-packaged optics (CPO), near-package optics (NPO), optical transceivers, or high-bandwidth connectivity solutions is a strong plus.

• Experience with advanced semiconductor technologies including CMOS, FinFET, BiCMOS, or SiGe.

• Strong understanding of semiconductor process technologies, device physics, and layout-dependent effects.

• Proficiency with Cadence Virtuoso and industry-standard EDA tools.

• Experience leveraging automation, scripting, or AI-assisted methodologies to improve layout productivity and quality.

• Solid understanding of layout techniques including matching, shielding, clock distribution, power planning, ESD protection, latch-up prevention, manufacturability, and reliability-aware design.

• Demonstrated success delivering complex layouts through tapeout.

• Ability to work effectively with globally distributed design, verification, CAD, and technology teams.

• Experience supporting multiple projects in a fast-paced product development environment.

Why Join Lumilens?

• Work alongside leaders and innovators in the photonics and semiconductor industry

• Opportunity to make an impact on the infrastructure powering next-generation AI and high-performance computing

• Fast-paced, collaborative, and mission-driven environment

• Competitive compensation and benefits

Join us at Lumilens and help shape the future of compute connectivity!