Sensor Subsystem RTL Design Engineer – SoC & Low Power

European Tech Recruit; Cork; On-site; EUR 80,000 - 105,000; Full time

Job summary

European Tech Recruit is partnering with a leading semiconductor company to hire a Sensor Subsystem Design Engineer. The role covers design, implementation, and verification of sensor subsystem IP within next-gen SoC platforms.

You will work across ASIC/RTL/low-power domains, using Verilog/SystemVerilog or VHDL, with AMBA interfaces, architecture discussions, and cross-functional collaboration to deliver robust silicon designs.

Qualifications

• Strong RTL development experience with Verilog, SystemVerilog, or VHDL.
• Solid understanding of digital design fundamentals.
• Knowledge of computer architecture and SoC concepts.
• Experience integrating digital hardware in complex semiconductor systems.
• Familiarity with AMBA interfaces (AHB, AXI, APB).

Responsibilities

• Contribute to the architecture, design, and development of ASIC and sensor subsystem components for next-gen SoC platforms.
• Develop high-quality RTL using Verilog, SystemVerilog, or VHDL.
• Translate architectural and subsystem requirements into robust, synthesizable digital designs.
• Contribute to the implementation and integration of sensor subsystem IP within complex SoC environments.
• Work with industry-standard AMBA interfaces including AHB, AXI, and APB.
• Support design verification activities throughout the development lifecycle.
• Participate in design reviews, architecture discussions, technical reviews, and cross-functional engineering meetings.
• Analyse and debug RTL and subsystem issues identified through simulation, verification, integration, or implementation.

Skills

Verilog/SystemVerilog/VHDL

Digital design fundamentals

SoC concepts

RTL development

AMBA (AHB/AXI/APB)

Job description

European Tech Recruit is partnering with a leading semiconductor company to hire a Sensor Subsystem Design Engineer. The role covers design, implementation, and verification of sensor subsystem IP within next-gen SoC platforms.

You will work across ASIC/RTL/low-power domains, using Verilog/SystemVerilog or VHDL, with AMBA interfaces, architecture discussions, and cross-functional collaboration to deliver robust silicon designs.