Senior Sensor ASIC Design Engineer — Low-Power SoC

Qualcomm; Cork; On-site; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Salary, stock bonus

Maternity/Paternity Leave

Employee stock purchase scheme

Relocation/immigration support

Life, Medical, Travel Insurance

Job summary

Qualcomm Cork is seeking an ASIC Engineer to define, model, design (digital/analog) and verify IP for high‑performance, low‑power devices. The role spans RTL coding, timing closure, and collaboration with software and systems teams on sensor‑based hardware for SoC integration in mobile applications.

The candidate will participate in the ASIC design flow from spec to netlist, with emphasis on sensor subsystems. A strong analytical background and leadership are valued.

Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• RTL design, System Verilog, Tcl/Perl/Python shell‑scripting skills.
• 1+ years of RTL design on‑chip with custom digital logic.
• Experience with ASIC ECO flow and Power/Timing checks is a plus.

Responsibilities

• Architecting, designing and implementing digital sensor hardware for ASIC SoC.
• Debugging, verifying, optimizing, and bit‑exact matching with test vectors.
• ASIC synthesis, static timing analysis and post‑RTL tooling for timing closure.
• Power estimation and low‑power design implementation.
• Collaborating with Software and Systems Engineering teams.
• Adherence to RTL/netlist release processes.
• Python automation and advancing workflow efficiency.
• Participate in project reviews and documentation.

Skills

RTL design

System Verilog

Python scripting

C++/SystemC

Education

Bachelor's degree in Science/Engineering

Tools

Primetime

PTPX

LEC

RTL Linting

Job description

Qualcomm Cork is seeking an ASIC Engineer to define, model, design (digital/analog) and verify IP for high‑performance, low‑power devices. The role spans RTL coding, timing closure, and collaboration with software and systems teams on sensor‑based hardware for SoC integration in mobile applications.

The candidate will participate in the ASIC design flow from spec to netlist, with emphasis on sensor subsystems. A strong analytical background and leadership are valued.