Senior Mixed-Signal IP Digital Design Engineer

Qualcomm; Ireland; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Stock bonus

Relocation support

Employee stock purchase scheme

Pension scheme

Education Assistance

Insurance (Life, Medical, Travel)

Well-being subsidies

Commuter benefits

Job summary

QT Technologies Ireland Limited is seeking experienced digital design engineers to contribute to Qualcomm MSIP projects. You will participate in architecture, RTL coding, front-end implementation, and collaborate with DV/PD teams for silicon bring-up and IP integration.

The role requires a Master’s in engineering with 5+ years in ASIC design, and hands-on use of Design Compiler, Fusion Compiler, Modelsim, VCS, Spyglass and Primetime. Excellent communication and teamwork are essential.

Qualifications

• Master's or equivalent in engineering; 5+ years in ASIC digital design.
• Experience with RTL design and front-end ASIC tools.
• Strong communication and collaboration skills.

Responsibilities

• Architecture, design, and implementation of digital sections of mixed-signal IPs.
• Apply DSP and optimization methods to improve PPA of IPs.
• Run full ASIC design tool suite to validate and implement designs.
• Collaborate with DV and PD teams for verification and physical implementation.
• Create design specifications and documentation.
• Support silicon bring-up and debugging with testing teams.

Skills

ASIC design

RTL design

Communication

Team collaboration

Education

Master's degree in Electrical/Computer Engineering

Bachelor's degree in Science/Engineering

Tools

Design Compiler

Fusion Compiler

Modelsim

VCS

Spyglass

Primetime

Job description

QT Technologies Ireland Limited is seeking experienced digital design engineers to contribute to Qualcomm MSIP projects. You will participate in architecture, RTL coding, front-end implementation, and collaborate with DV/PD teams for silicon bring-up and IP integration.

The role requires a Master’s in engineering with 5+ years in ASIC design, and hands-on use of Design Compiler, Fusion Compiler, Modelsim, VCS, Spyglass and Primetime. Excellent communication and teamwork are essential.