Senior MCU Subsystem Architect – SoC Leadership

QUALCOMM, Inc.

Cork

On-site

EUR 150,000 - 210,000

Full time

2 days ago

Be an early applicant

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Benefits offered by this job

Salary, stock and performance related?

Maternity/Paternity Leave

Employee stock purchase scheme

Matching pension scheme

Education Assistance

Relocation and immigration support

Life, Medical, Income and Travel

Subsidised memberships for physical/mt

Bicycle purchase scheme

Employee run clubs

Job summary

QT Technologies Ireland Limited in Cork is seeking a Senior Staff Engineer to provide deep technical leadership for the Microcontroller Sub-System IP, guiding architecture and RTL design across multiple business units including IoT, Mobile, Auto, and XR.

You will lead micro-architecture decisions, drive design quality, and mentor engineers while coordinating with DFT, Implementation, Verification, Emulation, and Firmware teams to optimize area, power, and performance.

Qualifications

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities

Micro-Architecture and Technical Leadership: Driving micro-architecture for both simple and highly complex digital blocks, making key design trade-offs, and providing technical leadership across the subsystem.
RTL Development and Design Quality: Leading RTL (Register Transfer Level) development using industry best practices. This includes handling multi-clock designs, high-frequency requirements, low power, and low latency considerations while ensuring high performance, scalability, and design robustness.
Debugging and Post-Silicon Bring-Up: Leading root-cause analysis and resolution of complex design issues during development and supporting post-silicon bring-up activities across cross-functional teams.
Documentation and Reviews: Creating comprehensive design documentation, driving high-quality design and architecture reviews, and ensuring clarity, maintainability, and reuse across projects.
Design Optimization: Driving optimization for key metrics such as area, power, and performance while balancing product requirements, implementation constraints, and long-term architectural goals.
Cross-Functional Collaboration and Mentorship: Partnering closely with DFT (Design for Testability), Implementation, Verification, Emulation, and Firmware teams, while mentoring junior engineers and influencing technical direction across the wider organization.