Senior Layout Engineering Manager - CMOS ICs

1020 ADBV Ireland; Limerick; On-site; EUR 120,000 - 150,000; Full time

Job summary

Analog Devices, Inc. is seeking a Senior Manager, Layout to guide a team of layout engineers tackling advanced CMOS FinFET designs (16nm and below) and to act as a technical authority on physical design of high-speed analog, mixed-signal, and digital subsystems.

You will drive floorplanning, mentor engineers, collaborate with DFT, timing, power, RTL, and packaging, and define design methodologies and automation workflows to ensure successful tapeout and on-time milestones.

Qualifications

• Industry‑leading IC layout expertise required.
• Strong leadership and ability to mentor engineers.
• Proven ability to drive design closures and cross-functional collaboration.

Responsibilities

• Lead a team of layout engineers in advanced CMOS FinFET technologies (16nm and below).
• Physical design lead of high-speed/analog/mixed-signal/digital subsystems (ADCs, DACs, PLLs, transceivers).
• Drive floorplan development at block, subsystem, and full-chip levels for large designs.
• Collaborate with DFT, clock, timing, power integrity, RTL, packaging, and analog designers for seamless integration and closure.
• Define, implement, and improve design methodologies, best practices, and automation workflows; promote knowledge sharing.
• Lead physical verification processes including DRC, LVS, ERC, density checks, extraction, EM/IR analysis, and tapeout signoff.
• Develop project schedules, monitor progress, and ensure on-time delivery of milestones.
• Mentor and lead layout teams, fostering technical growth and project success.

Skills

Technical authority

Layout expertise

Collaboration

Leadership

Education

Bachelors in Electrical/Computer Engineering

Tools

Cadence Virtuoso

Job description

Analog Devices, Inc. is seeking a Senior Manager, Layout to guide a team of layout engineers tackling advanced CMOS FinFET designs (16nm and below) and to act as a technical authority on physical design of high-speed analog, mixed-signal, and digital subsystems.

You will drive floorplanning, mentor engineers, collaborate with DFT, timing, power, RTL, and packaging, and define design methodologies and automation workflows to ensure successful tapeout and on-time milestones.