Lead Software Engineer - Compiler/LLVM

Cadence; Cork; On-site; EUR 70,000 - 90,000; Full time

Benefits offered by this job

25 days holiday per year

Private Medical and Dental plans

Group Personal Pension Plan

Gym subsidy

Employee Stock Purchase Plan

Job summary

Cadence is seeking a Lead Software Engineer specialized in Compiler/LLVM for our Cork, Ireland location. This role involves designing and implementing optimisations and features for Xtensa processors, collaborating closely with hardware teams.

The ideal candidate will have a degree in Computer Science or Electrical Engineering and at least 4 years of experience in compiler development, preferably with strong C/C++ skills. The position offers a competitive salary, 25 days of holiday, and comprehensive medical benefits.

Qualifications

• 4+ years of experience in compiler development or low-level systems software.
• Strong foundation in computer architecture and performance optimisation.

Responsibilities

• Design and implement compiler optimisations for Xtensa processors.
• Analyse and optimise real-world workloads including AI, DSP, and vision.

Skills

C/C++ programming skills

Debugging and problem-solving skills

Understanding of compiler internals

Education

Bachelor’s or Master’s degree in Computer Science, Electrical Engineering

Tools

LLVM

GCC

Job description

Job Title: Lead Software Engineer – Compiler/LLVM

Location: Cork, Ireland or Belo Horizonte, Brazil

Reports to: Sr Software Architect

Job Overview

Tensilica, a Cadence company, delivers configurable processor IP and DSP solutions powering AI, vision, audio, and communications workloads. Its Xtensa architecture enables highly optimized, domain-specific designs with industry-leading performance and efficiency. The C Compiler team builds the toolchain that unlocks this performance. Working on LLVM‑based compilers for Xtensa processors, the team drives code generation, architecture‑aware optimizations, and real‑world workload performance. In close partnership with hardware teams, they enable new capabilities and deliver production‑grade tools used by leading semiconductor and systems companies.

Responsibilities

• Design and implement compiler optimisations and features for Xtensa processors
• Drive improvements in code generation, performance tuning, and architecture enablement across the toolchain
• Partner closely with hardware and architecture teams on new ISA features and capabilities
• Analyse and optimise real‑world workloads, including AI, DSP, and vision use cases
• Provide technical mentorship to junior engineers and contribute to the team’s technical direction and best practices

Requirements

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field (or equivalent practical experience)
• Typically 4+ years of experience in compiler development or low‑level systems software (academic or industry experience considered)
• Strong C/C++ programming skills with solid debugging and problem‑solving expertise
• Good understanding of compiler internals (LLVM, GCC, or similar frameworks)
• Strong foundation in computer architecture and performance optimisation

Nice To Have

• Experience with DSPs, AI/ML workloads, or embedded systems
• Hands‑on experience with LLVM or GCC backends and optimisation passes
• Experience working close to hardware teams or enabling new processor architectures

What We Can Offer You

• Competitive salary
• 25 days holiday per year
• Private Medical and Dental plans, Income Protection and Life Insurance
• Group Personal Pension Plan
• Cycle to work scheme and gym subsidy
• 5 days paid time to volunteer to give back to our communities
• Employee Stock Purchase Plan
• The opportunity to work for a Great Place to Work & Fortune 100 organization

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

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