Wireless SoC Low Power Design Engineer

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Wireless SoC Low Power Design Engineer, Irvine

Client:

Apple

Location:

Irvine, United Kingdom

Job Category:

-

EU work permit required:

Yes

Job Reference:

98dbd11a94e2

Job Views:

3

Posted:

18.04.2025

Expiry Date:

02.06.2025

Job Description:

Summary:
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

Key Qualifications:

1. 5+ years of experiences in Low Power ASIC design and SOC integration
2. Proficiency in ASIC logic design
3. Extensive experience with SoC power management design including power gating, isolation, retention and DVFS techniques
4. SoC level clock mesh / reset design experience desirable
5. Proficiency in scripting languages (Shell and Perl highly desirable, Python skills are a plus)
6. Deep understanding of ASIC low power design techniques, e.g. Power analysis, UPF, VCLP
7. Hands on experience with PTPX and Power Artist power analysis tools is a plus
8. System architecture knowledge is a bonus
9. Silicon validation / power measurement experience is a plus

1. Drive SoC low power micro-architecture, definition, implementation, and analysis
2. Own complex SoC power management, boot flow, clock and reset management
3. Write micro-architecture specifications and design specifications
4. Design, implement, and debug complex logic designs
5. Integrate complex IPs into SoC
6. Run tools to ensure lint-free and CDC clean design
7. Support all front end design and integration activities such as synthesis and timing constraints
8. Support pre and post silicon validation

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Created on 18/04/2025 by TN United Kingdom