TPU Performance Engineer - vLLM Inference Backends

INFERACT SINGAPORE PTE. LTD.; Penarth; On-site; GBP 99,000 - 198,000; Full time

Benefits offered by this job

Equity

Medical coverage

Dental coverage

Vision coverage

Job summary

Inferact Singapore PTE. LTD. is seeking a TPU performance engineer to make vLLM a first-class inference engine on Google TPUs.

You will build and optimize TPU backends, compiler integrations, runtime paths, and benchmarking infrastructure using JAX, XLA, Pallas, and related tooling so vLLM can deliver frontier inference performance on TPU hardware. You'll work at the boundary of inference systems, kernels, compilers, and hardware architecture, improving production-relevant model serving on TPU

Qualifications

• Bachelor's degree or equivalent experience in computer science, engineering, systems, machine learning, or similar.
• Hands-on experience building or optimizing TPU workloads using JAX, XLA, Pallas, or related compiler and runtime tooling.
• Deep understanding of TPU execution, memory behavior, compilation, and performance constraints for ML workloads.
• Experience optimizing ML kernels or inference paths such as attention, GEMM, sampling, KV cache, fused kernels, or backend runtime paths.
• Strong performance profiling and benchmarking skills, with the ability to use measurements, compiler artifacts, correctness tests, and reproducible benchmarks to guide optimization work.

Skills

TPU workloads

JAX/XLA experience

Performance profiling

ML kernel optimization

Benchmarking

Education

Bachelor's degree or equivalent experience

Tools

Pallas

XLA tooling

Job description

Inferact Singapore PTE. LTD. is seeking a TPU performance engineer to make vLLM a first-class inference engine on Google TPUs.

You will build and optimize TPU backends, compiler integrations, runtime paths, and benchmarking infrastructure using JAX, XLA, Pallas, and related tooling so vLLM can deliver frontier inference performance on TPU hardware. You'll work at the boundary of inference systems, kernels, compilers, and hardware architecture, improving production-relevant model serving on TPU