Staff AMD GPU Performance Engineer, Inference Acceleration

INFERACT SINGAPORE PTE. LTD.; Penarth; On-site; GBP 99,000 - 198,000; Full time

Benefits offered by this job

Equity

Medical coverage

Yearly bonus

Job summary

Inferact is seeking an AMD GPU performance engineer to advance vLLM as a premier inference engine on AMD accelerators. You will build and optimize AMD GPU backends, kernels, and benchmarking infrastructure using ROCm, HIP, Triton, CK, and AITER.

You will work at the boundary of inference systems, kernels, compilers, and hardware, improving attention, GEMM, sampling, KV cache, and other communication-heavy paths to deliver fast, scalable inference and maintainable backend.

Qualifications

• Bachelor's degree or equivalent in CS, engineering, systems, ML, or similar.
• Hands-on experience optimizing AMD GPU workloads using ROCm, HIP, Triton, CK, AITER, or similar tools.
• Deep understanding of AMD GPU execution, memory behavior, toolchains, kernel performance, and backend constraints.
• Experience optimizing ML kernels or inference paths (attention, GEMM, sampling, KV cache, fused kernels, or heavy-communication paths).
• Strong performance profiling with measurements, hardware counters, correctness tests, and reproducible benchmarks.

Responsibilities

• Build and optimize AMD GPU backends, kernels, runtime paths, and benchmarking infrastructure using ROCm, HIP, Triton, CK, AITER, and related tooling.
• Improve performance-critical paths such as attention, GEMM, sampling, KV cache, and communication-heavy operations to enable fast, maintainable backend for vLLM.

Skills

ROCm

HIP

Triton

CK

AITER

Performance profiling

ML kernels

Education

Bachelor's degree or equivalent

Tools

vLLM

TensorRT-LLM

LLVM

MLIR

Job description

Inferact is seeking an AMD GPU performance engineer to advance vLLM as a premier inference engine on AMD accelerators. You will build and optimize AMD GPU backends, kernels, and benchmarking infrastructure using ROCm, HIP, Triton, CK, and AITER.

You will work at the boundary of inference systems, kernels, compilers, and hardware, improving attention, GEMM, sampling, KV cache, and other communication-heavy paths to deliver fast, scalable inference and maintainable backend.