Staff Verification Engineer (f/m/div)

Infineon Technologies; Bristol; On-site; GBP 55,000 - 75,000; Full time

Job summary

A leading company in the semiconductor industry is seeking a Staff Verification Engineer to join their team in Bristol. This role involves developing testbenches, leading verification strategies, and contributing to a dynamic team environment. Ideal candidates should possess a degree in Electrical Engineering and have substantial verification experience, particularly with System Verilog - UVM.

Benefits

Mentoring and networking opportunities

Training and career development options

Flexible working conditions, including part-time options

Sabbatical, medical coverage, private insurance, pension benefits

Performance bonuses and awards

Qualifications

• At least 3 years of verification experience, preferably at the IP level.
• Advanced knowledge of UVM, SVAs, and System Verilog.
• Ability to interpret complex design specifications.

Responsibilities

• Developing System Verilog - UVM testbenches and solving complex problems.
• Leading the development of new SV UVM verification components.
• Participating in reviews to ensure quality and completeness of test benches.

Skills

System Verilog - UVM

Verification

Debugging

Communication

Time Management

Education

Bachelor's degree in Electrical/Electronic Engineering

Tools

EDA tools

PC Lint

SVN

Git

Job description

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Client:

Infineon Technologies

Location:

Bristol, United Kingdom

Job Category:

Other

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EU work permit required:

Yes

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Job Reference:

ea7a5e78b918

Job Views:

4

Posted:

02.07.2025

Expiry Date:

16.08.2025

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Job Description:

Are you a passionate engineer eager to join a verification team using leading-edge tools and methodologies? Do you want to be part of the growth of our Design Center in Bristol and play a key role at the #1 semiconductor partner in the automotive industry? Join us as a Staff Verification Engineer and contribute to our success story.

Your responsibilities will include:

• Developing System Verilog - UVM testbenches and solving complex problems related to test bench development
• Leading the development of new SV UVM verification components
• Understanding and modifying Specman-e test benches
• Debugging failing test cases
• Defining and writing functional coverage models
• Participating in reviews to ensure quality and completeness of test benches
• Contributing to verification strategies in design meetings
• Ensuring test benches meet sign-off targets, including coverage and safety
• Enhancing verification strategies and architectures for IP test benches

We value a team player who is proactive, communicative, detail-oriented, and committed to exceeding customer expectations.

Ideal candidates will have:

• Bachelor's degree in Electrical/Electronic Engineering or equivalent
• At least 3 years of verification experience, preferably at the IP level, with System Verilog - UVM; knowledge of Specman-e is a plus
• Advanced knowledge of UVM, SVAs, and System Verilog
• Experience with verification platform and framework development
• Ownership of IP verification including meeting metrics
• Ability to interpret complex design specifications
• Proficiency with industry-standard EDA tools
• Good time management and ability to deliver under pressure
• Clear communication skills in English
• A safety-first approach with attention to detail

Additional beneficial skills include:

• Knowledge of functional safety and scripting languages
• Experience with tools like PC Lint, SVN, Git, etc.

Please send your CV in English.

Benefits include:

• Mentoring and networking opportunities
• Training and career development options
• Various career paths: Project Management, Technical Ladder, Management, Individual Contributor
• Flexible working conditions, including part-time options
• Sabbatical, medical coverage, private insurance, pension benefits
• Performance bonuses and awards
• Accessible facilities