SoC Design Architect (ASIC Digital Systems)

JR United Kingdom; Cambridgeshire and Peterborough; On-site; GBP 75,000 - 90,000; Full time

Job summary

An innovative semiconductor company is seeking a SOC Design Architect to lead exciting new projects. This role involves overseeing the complete SOC architecture for cutting-edge chips, ensuring high performance and low power consumption. Ideal candidates will have extensive experience in digital IC design and SOC architecture, along with a strong educational background in micro-electronics or physics. Join a dynamic team and contribute to groundbreaking technology that shapes the future of the industry!

Qualifications

• 5-10 years' experience in digital IC design and SOC architecture.
• Deep understanding of MCUs, Memory Controllers, and memory architectures.

Responsibilities

• End-to-end SOC architecture of new chips for innovative products.
• Engage in full chip design and delivery to tape-out.

Skills

Digital IC Design

SOC Architecture

RTL Design

Debug Methodologies

Low-Power Optimization

DSP/Signal Processing

Education

BSc in Micro-electronics

MSc in Physics

PhD in similar field

Job description

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Client:

IC Resources

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Job Category:

Other

EU work permit required:

Yes

Job Views:

15

Posted:

28.04.2025

Expiry Date:

12.06.2025

Job Description:

Working for a cutting-edge semiconductor company, I am looking to recruit a SOC Design Architect for fascinating and brand-new project work.

The position is available for engineers / applicants who can demonstrate experience of full chip design, (plus understanding / experience of) architecture and delivery (to tape-out).

Salary available is dependent on years of experience - circa £75-90k, with excellent package and benefits.

Based in Cambridgshire, you will be tasked with the end to end SOC architecture of new chips for brand new products in the market.

• BSc / MSc / PhD in Micro-electronics, physics, or similar field
• Approx 5-10 years' experience in digital IC design and SOC architecture
• Deep understanding of MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, eFuse).
• Extensive experience with the Digital ASIC Flow, RTL design, and Debug methodologies (e.g., DFT, JTAG, Scan, BIST).
• Extensive knowledge of SOC architecture, set-up / silicon bring-up, validation and all its associated processes.
• IP selection & top level integration
• SOC performance & modelling e.g. UML
• DSP / signal processing / communication protocols
• Digital-AMS chip development - digital to analog interfaces
• Low-power, performance and optimization
• Low level software, firmware and embedded requirements - drivers, controllers etc.