Senior UVM Digital Verification Engineer - Hybrid

ZipRecruiter; Cambridge; Hybrid; GBP 60,000 - 90,000; Full time

Job summary

A leading technology company is seeking a Senior UVM Digital Verification Engineer to join their dynamic Digital Design Team. The role involves developing advanced verification strategies for complex FPGA and ASIC designs while collaborating with multidisciplinary teams. Candidates should possess extensive experience in SystemVerilog and UVM, demonstrating strong analytical and problem-solving skills. This position offers a hybrid work model with a focus on critical systems in embedded security and communications.

Qualifications

• 5-15 years of experience in digital verification.
• Deep experience with UVM/UVMF and industry simulators.
• Experience integrating modeling tools.

Responsibilities

• Develop verification and test plans for digital designs.
• Collaborate with RTL designers to resolve simulation issues.
• Analyze technical risks and contribute to system engineering.

Skills

SystemVerilog

UVM/UVMF

Python

Perl

Bash

Mathematical skills

Problem-solving

Linux

Education

Bachelor's degree in Aerospace, Electrical, Mechanical, or related engineering field

Master’s degree

Tools

SysML

MATLAB/Simulink

Job description

Job DescriptionJob Description

Senior UVM Digital Verification Engineer – Hybrid
Location: Cambridge, MA
Work Model: Hybrid (Minimum 3 days in office per week)
Employment Type: Full-Time
Seniority Level: Mid-Senior Level

Overview
Our client’s Digital Design Team is seeking a Senior UVM Digital Verification Engineer to develop and apply cutting-edge verification strategies for complex FPGA and ASIC designs. This position offers the opportunity to work on critical systems in embedded security, cryptography, signal and image processing, navigation, and communications.

Key Responsibilities

• Develop verification and test plans for digital and mixed-signal designs
  

• Build and maintain UVM agents and instantiate VIPs for standard/proprietary buses
  

• Execute block-level and chip-level UVM testbenches
  

• Collaborate with RTL designers to resolve simulation issues
  

• Implement and manage cover groups to meet 100% functional/code coverage
  

• Lead small teams and mentor junior engineers
  

• Analyze technical risks and contribute to system engineering lifecycle activities
  

• Translate system requirements into architectural and design decisions
  

• Support integration and test activities in a multidisciplinary environment
  

Requirements

Technical Requirements

• Fluent in SystemVerilog, including SystemVerilog Assertions (SVA)
  

• Deep experience with UVM/UVMF and industry simulators (e.g., Questasim, Xcelium, VCS)
  

• Knowledge of protocols such as AXI, DDR3/DDR4
  

• Proficiency with scripting (e.g., Python, Perl, Bash)
  

• Strong background in constrained-random testing and coverage-driven verification
  

• Familiarity with formal analysis tools
  

• Comfortable working in Linux environments
  

General Skills

• Excellent mathematical and problem-solving skills
  

• Strong written and verbal communication skills
  

• Demonstrated ability to mentor and collaborate across teams
  

• Ability to work independently and manage changing priorities
  

• Skilled in using MBSE tools (e.g., SysML) and simulation platforms (MATLAB/Simulink)
  

Education & Experience

• Bachelor's degree in Aerospace, Electrical, Mechanical, or related engineering field (Master’s )
  

• 5–15 years of experience in digital verification, system analysis, or a related field
  

• Experience integrating modeling tools and developing multi-domain models
  

Additional Requirements

• Applicants must be U.S. citizens or permanent
  

• Must be able to obtain and maintain a government security clearance
  

Job Details

• Experience Required: 5–15 years
  

• Work Schedule: Full-time, hybrid (3+ days in office)
  

• Location: Cambridge, MA
  

• Number of Openings: 1