Senior Test Engineer — High-Speed Mixed-Signal/Rf (V93000, 200Gbps+)

Semtech; West of England; Hybrid; GBP 90,000 - 130,000; Full time

Job summary

Semtech Bristol Design Centre is seeking a senior test engineering leader to become the technical authority for test development across our mixed-signal and RF portfolio. You will design test strategies for 200Gbps+ SerDes and CDR architectures, from wafer to volume production, and set DFT standards the organisation adopts.

Your background includes Advantest V93000, signal integrity, jitter, and BER analysis, plus experience leading NPI programs and driving continuous improvement in test

Qualifications

• 8+ years of semiconductor test engineering experience, including 4+ years in mixed-signal/RF test development.
• Proven track record leading NPI programs for high-speed ICs.
• Expert level with Advantest V93000 platform (SmarTest 7/8).
• Advanced programming in C/C++, Python, and TCL.
• Strong knowledge of high-speed signal integrity, jitter, and BER testing.
• Experience with RF/microwave test techniques beyond 40GHz.
• Experience with PCB design tools (Cadence, Altium).

Responsibilities

• Architect test strategies for complex mixed-signal / RF products from concept through production maturity.
• Lead development of innovative test methodologies for high-speed SerDes, CDRs, and signal conditioning products.
• Drive DFT/testability requirements into IC architecture, establishing company-wide standards and best practices.
• Develop and implement advanced test techniques for products operating at >200Gbps data rates.
• Create reusable test IP, libraries, and frameworks that accelerate NPI cycles across product families.
• Perform technical risk assessment and mitigation strategies for test coverage and quality.

Skills

Mixed-signal test

RF test techniques

Python

C/C++

TCL

Jitter analysis

BER testing

Signal integrity

DFT techniques

Problem solving

Project leadership

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering or related field

PhD (preferred)

Tools

Advantest V93000 (SmarTest 7/8)

Cadence

Altium

Wafer-level test equipment

Job description

Location

Bristol, UK — Semtech Bristol Design Centre

Hybrid Working

Monday – Thursday (Friday Flexible)

Our Team

When a 200Gbps+ SerDes or a cutting-edge RF SiGe device needs to prove it's production-ready, our Global Test Engineering team is the reason it gets there. We don't just run tests; we architect the methodologies, the IP, and the standards the rest of the engineering organisation builds on.

Job Summary

This is a rare one: the chance to become the technical authority for test development across Semtech's entire mixed-signal and RF portfolio. We need someone who can look at a 200Gbps+ SerDes or CDR architecture and know exactly how to prove it works — at wafer level, at package level, and at volume. You'll architect comprehensive test strategies from first silicon through to mass production, set the DFT and testability standards the wider organisation adopts, and lead the methodologies behind some of the most demanding high-speed communication products in the industry. If your background spans Advantest V93000 architecture, SiGe BiCMOS test challenges, and the kind of signal integrity, jitter and BER analysis most engineers only read about in papers — this is the seat where that expertise finally gets to lead, not just support.

Responsibilities

Here's where your expertise takes the lead:

Technical Leadership & Architecture

• Architect and define test strategies for complex mixed-signal / RF SiGe products from concept through production maturity
• Lead development of innovative test methodologies for high-speed SerDes, CDRs, and signal conditioning products
• Drive DFT/testability requirements into IC architecture, establishing company-wide standards and best practices
• Develop and implement advanced test techniques for products operating at >200Gbps data rates
• Create reusable test IP, libraries, and frameworks that accelerate NPI cycles across product families
• Perform technical risk assessment and mitigation strategies for test coverage and quality

Cross-functional NPI Support

• Serve as test engineering authority in product architecture reviews and gate meetings
• Partner with IC design teams from concept phase to ensure optimal test coverage and manufacturability
• Lead test readiness reviews with stakeholders, providing strategic recommendations
• Collaborate with Product Engineering to define characterization strategies and correlation methodologies
• Interface with customer quality teams on test specifications and coverage requirements
• Architect and launch test solutions that achieve test time targets for complex mixed-signal / RF devices
• Drive continuous improvement initiatives that reduce NPI cycle time by 10–20%

Production Excellence & Scale

• Ensure seamless transfer of test solutions to high-volume OSATs with >99% first-pass success
• Drive test cost reduction initiatives delivering year-over-year improvements
• Establish and monitor KPIs for test effectiveness, efficiency, and quality

Mentorship & Knowledge Management

• Mentor junior engineers, developing the next generation of test engineering contributors
• Create and maintain comprehensive test methodology documentation and training materials
• Build strategic relationships with test partners to influence platform development
• Foster a culture of innovation and continuous learning within the test organisation

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 8+ years of progressive experience in semiconductor test engineering, including 4+ years specifically in mixed-signal/RF test development
• Proven track record leading NPI programs for high-speed communication ICs
• Expert-level proficiency with the Advantest V93000 platform (SmarTest 7/8)
• Advanced programming skills in C/C++, Python, and TCL
• Deep understanding of high-speed signal integrity, jitter analysis, and BER testing
• Expertise in analog/mixed-signal DFT techniques (BIST, scan, boundary scan)
• Proficiency in RF/microwave test techniques beyond 40GHz
• Strong foundation in statistical process control and quality methodologies
• Experience with PCB design tools (Cadence, Altium) and signal integrity simulation
• Demonstrated ability to influence without direct authority across organisations
• Track record of delivering complex projects on aggressive schedules
• Strong presentation skills to executive leadership and customers

Desired Qualifications

• Master's degree or PhD in a relevant engineering discipline
• 8+ years in semiconductor test with a focus on SerDes/high-speed I/O
• Experience with SiGe BiCMOS process technology and its test challenges
• Knowledge of automotive quality standards (AEC-Q100) and qualification flows
• Familiarity with 93000 PS1600/PS5000 digital channels and Wave Scale RF
• Experience with wafer-level testing and probe card design
• Experience with test data analytics and machine learning applications

Why Join Us?

• Be the name people associate with test architecture for mixed-signal/RF products company-wide — a reputation, not just a function
• Shape test capability that opens entirely new markets — your work becomes the reason new product categories are even possible
• Operate at the genuine bleeding edge — 200Gbps+ data rates — inside a global centre of excellence, not a regional side project
• Build something that outlives the project: reusable test IP, frameworks and standards the next five product generations will run on
• Join a team with the scale and ambition to match your expertise, not one that will under-use it

Career Growth Philosophy: At Semtech, we believe innovation starts with people. We're committed to developing engineers who combine deep technical expertise with real organisational influence — this role is a direct route into test architecture leadership, with the scope to shape standards that the wider engineering organisation adopts.

Additional Notes

The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.