Senior Power Integrity Engineer for AI Networking Platforms

DriveNets; Greater London; On-site; GBP 89,000 - 133,000; Full time

Job summary

DriveNets is seeking a highly motivated Senior Power Integrity Engineer to join our Hardware Engineering team. You will define, analyze, simulate, and validate power delivery networks for next-generation networking platforms supporting high-performance ASICs and SerDes interfaces.

You will collaborate with hardware architects, PCB designers, ASIC teams, signal integrity engineers, and manufacturing partners to ensure robust PI, validate requirements, and drive PDN reliability across the product

Qualifications

• B.Sc. or M.Sc. in Electrical Engineering required.
• 5+ years of experience in Power Integrity, Hardware Design, or related disciplines.
• Strong understanding of power delivery networks, decoupling methodologies, and target impedance concepts.
• Hands-on experience with PI simulation tools listed above.
• Experience designing high-layer-count PCBs for networking, telecom, server, or data-center products.
• Knowledge of high-speed digital systems and interaction between Signal Integrity and Power Integrity.
• Experience with multi-phase voltage regulators, power sequencing, and power management architectures.
• Strong understanding of PCB materials, stackups, and manufacturing constraints.
• Experience performing lab validation and correlation measurements.
• Excellent problem-solving, communication, and teamwork skills.

Responsibilities

• Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
• Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
• Perform pre-layout and post-layout PI simulations using industry-standard tools.
• Establish target impedance requirements and validate compliance across all power rails.
• Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
• Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
• Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
• Develop power integrity design guidelines and best practices for next-generation networking products.
• Support schematic reviews, layout reviews, and design sign-off activities.
• Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
• Investigate and resolve PI-related issues during board bring-up, validation, and production.
• Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
• Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

Skills

Power integrity

Hardware design

PDN analysis

High-speed PCB design

Lab validation

Multi-phase regulators

Education

B.Sc. or M.Sc. in Electrical Engineering

Tools

Cadence Sigrity PowerSI/OptimizePI

Ansys SIwave

Ansys HFSS

PowerDC

Job description

DriveNets is seeking a highly motivated Senior Power Integrity Engineer to join our Hardware Engineering team. You will define, analyze, simulate, and validate power delivery networks for next-generation networking platforms supporting high-performance ASICs and SerDes interfaces.

You will collaborate with hardware architects, PCB designers, ASIC teams, signal integrity engineers, and manufacturing partners to ensure robust PI, validate requirements, and drive PDN reliability across the product