Senior Member of Engineering

ZipRecruiter; London; On-site; GBP 70,000 - 90,000; Full time

Job summary

A leading engineering firm in London is seeking a Senior Member of Engineering Staff to design FPGAs for defense applications. This role requires a strong background in FPGA design and VHDL, along with the ability to work with advanced engineering methodologies. The ideal candidate will have excellent communication skills and an active DoD Security Clearance. Various benefits are offered.

Benefits

Health and insurance

401(k) match

Flexible spending accounts

Education assistance

Paid time off

Company-paid holidays

Qualifications

• Bachelor of Science (BS) or higher in relevant engineering field.
• 3-5+ years of FPGA design experience with VHDL.
• Experience with Xilinx FPGAs and revision control systems.

Responsibilities

• Derive FPGA design specifications from system requirements.
• Develop detailed FPGA architecture for implementation.
• Perform module-level simulations and validate design.

Skills

FPGA design experience with VHDL

Strong written and verbal communication

Proficiency in C++ (OOP)

Active DoD Security Clearance

Education

Bachelor of Science (BS) or Master (MS) or PhD in relevant field

Tools

Xilinx FPGAs and Vivado

Revision control systems

Job description

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands-on design/debug with primarily Ethernet, I2C, SPI, AXI protocols.

This employer utilizes state-of-the-art EDA flows/methodologies, including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization capable of targeting all FPGA vendors and have ASIC front-end capabilities with mature design processes.

This is a high-impact role in the organization to ensure robust quality and delivery of communication products for Security.

Essential Functions:

1. Derive FPGA design specifications from system requirements
2. Develop detailed FPGA architecture for implementation
3. Implement design in RTL (VHDL) and perform module-level simulations
4. Perform Synthesis, Place and Route (PAR), and Static Timing Analysis (STA)
5. Ensure RTL quality using: Lint, RDC, CDC, Static Formal EDA
6. Generate verification test plans and perform End-to-End Simulations
7. Support Board and FPGA bring-up
8. Validate design through HW/SW integration testing with test equipment
9. Support product collateral for NSA certification

Qualifications:

• Bachelor of Science (BS) or Master (MS) or PhD in engineering, engineering technology, chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Science from an accredited institution
• 3-5+ years of FPGA design experience with VHDL
• Experience with Xilinx FPGAs and Vivado
• Experience with revision control systems
• Experience with Earned Value Management (EVM)
• Strong written, verbal, and presentation skills
• Active DoD Security Clearance

Additional Skills:

• Experience mapping algorithms to architecture
• Proficiency in C++ (OOP)
• Experience with protocols such as Ethernet, TCP/IP, PCIe, NVMe, USB
• Experience with Xilinx SoC design, SDKs, and PetaLinux OS
• Experience with High-Level Synthesis (HLS) using Vivado HLX or Mentor Catapult

This employer offers various benefits, including health and insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. Benefits may vary depending on hire date, schedule, and collective bargaining agreements.