Senior Machine Learning Applications and Compiler Engineer, LPX

NVIDIA; United Kingdom; Sur place; GBP 60 000 - 90 000; Plein temps

Résumé du poste

A leading technology firm in the UK is seeking engineers to develop algorithms and optimizations for their LPX inference and compiler stack. You will maintain high-performance components and collaborate closely with hardware teams to impact future architectures. Ideal candidates should have a strong software engineering background, proficiency in systems programming, and experience in compiler development. Join to contribute to cutting-edge technology and help shape the future of AI systems.

Qualifications

• 5 years of relevant experience in compiler or runtime development.
• Proficiency in data structures, algorithms, and concurrency.
• Solid understanding of performance profiling and benchmarking tools.

Responsabilités

• Develop algorithms and optimizations for LPX inference and compiler stack.
• Maintain high-performance runtime and compiler components.
• Collaborate with hardware architects for architecture feedback.
• Publish technical work on compilation approaches at major venues.

Connaissances

Systems level programming (C/C++ or Rust)

Compiler or runtime development

Deep learning frameworks (TensorFlow, PyTorch)

Parallel and heterogeneous compute architectures

Analytical and debugging skills

Formation

MS or PhD in Computer Science or related field

Outils

LLVM

MLIR

Description du poste

NVIDIA is seeking engineers to develop algorithms and optimizations for our LPX inference and compiler stack. You will work at the intersection of large-scale systems, compilers, and deep learning, crafting how neural network workloads map onto future NVIDIA platforms. This is your chance to be part of something outstandingly innovative!

What You’ll Be Doing

• Build, develop, and maintain high-performance runtime and compiler components, focusing on end-to-end inference optimization.
• Define and implement mappings of large-scale inference workloads onto NVIDIA’s systems.
• Extend and integrate with NVIDIA’s SW ecosystem, contributing to libraries, tooling, and interfaces that enable seamless deployment of models across platforms.
• Benchmark, profile, and monitor key performance and efficiency metrics to ensure the compiler generates efficient mappings of neural network graphs to our inference hardware.
• Collaborate closely with hardware architects and design teams to feedback software observations, influence future architectures, and codesign features that unlock new performance and efficiency points.
• Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors.
• Publish and present technical work on novel compilation approaches for inference and related spatial accelerators at top tier ML, compiler, and computer architecture venues.

What We Need To See

• MS or PhD in Computer Science, Electrical/Computer Engineering, or related field, or equivalent experience, with 5 years of relevant experience.
• Strong software engineering background with proficiency in systems level programming (e.g., C/C++ and/or Rust) and solid CS fundamentals in data structures, algorithms, and concurrency.
• Hands on experience with compiler or runtime development, including IR design, optimization passes, or code generation.
• Experience with LLVM and/or MLIR, including building custom passes, dialects, or integrations.
• Familiarity with deep learning frameworks such as TensorFlow and PyTorch, and experience working with portable graph formats such as ONNX.
• Solid understanding of parallel and heterogeneous compute architectures, such as GPUs, spatial accelerators, or other domain specific processors.
• Strong analytical and debugging skills, with experience using profiling, tracing, and benchmarking tools to drive performance improvements.
• Excellent communication and collaboration skills, with the ability to work across hardware, systems, and software teams.
• Ideal candidates will have direct experience with MLIR based compilers or other multilevel IR stacks, especially in the context of graph based deep learning workloads.

Ways To Stand Out From The Crowd

• Prior work on spatial or dataflow architectures, including static scheduling, pipeline parallelism, or tensor parallelism at scale.
• Contributions to open-source ML frameworks, compilers, or runtime systems, particularly in areas related to performance or scalability.
• Demonstrated research impact, such as publications or presentations at conferences like PLDI, CGO, ASPLOS, ISCA, MICRO, MLSys, NeurIPS, or similar.
• Experience with large-scale AI distributed inference or training systems, including performance modeling and capacity planning for multi rack deployments.