Senior Low-Latency Risk Engine Lead

Citigroup Inc.; Greater London; Hybrid; GBP 120,000 - 180,000; Full time

Benefits offered by this job

27 days annual leave

Discretionary bonus

Private medical care

Life Insurance

Pension plan

Job summary

Citi is seeking a Senior Software Engineer – Ultra Low Latency Risk Engine Lead Developer to design, develop, and deliver a next-generation risk engine for cash equities trading. You will work across global teams, mentoring engineers and driving architecture decisions to ensure microsecond-level performance and robust risk controls.

The role combines hands-on engineering with leadership, mentoring, and cross-functional coordination across product, quant research, and infrastructure.

Qualifications

• Extensive software engineering experience in latency-critical systems for cash equities trading.
• Strong expertise in Low Latency Java and/or C++ with JVM/GC tuning.
• Experience with Aeron/Solace messaging frameworks and high-throughput trading systems.
• Leadership experience managing or leading engineering teams (onshore/offshore).

Responsibilities

• Design, develop, and maintain ultra-low-latency risk engine components in cash equities trading.
• Lead architecture decisions and coordinate delivery across global teams.
• Collaborate with product, quants, infrastructure, and QA to embed risk checks in the trade lifecycle.
• Build deterministic tests and CI/CD pipelines for latency-sensitive systems.
• Mentor engineers and drive technical roadmap for risk engine and low-latency paths.
• Provide production support and root-cause analysis for performance regressions.

Skills

Low Latency Java

C++

Multi-threading

JVM tuning

Performance tuning

Aeron

Solace

Shared memory IPC

RDMA

Tools

Aeron

Solace

Shared memory IPC

RDMA

Job description

Citi is seeking a Senior Software Engineer – Ultra Low Latency Risk Engine Lead Developer to design, develop, and deliver a next-generation risk engine for cash equities trading. You will work across global teams, mentoring engineers and driving architecture decisions to ensure microsecond-level performance and robust risk controls.

The role combines hands-on engineering with leadership, mentoring, and cross-functional coordination across product, quant research, and infrastructure.