Senior GPU Verification Engineer — UVM & SystemVerilog

Imagination Technologies Limited; Kings Langley; On-site; GBP 65,000 - 90,000; Full time

Job summary

Imagination Technologies Limited is seeking a hardware verification engineer to design verification plans and build UVM testbenches for cutting-edge PowerVR designs. You will own task definitions, estimates, and progress, while contributing to GPU verification methodology improvements and coverage reporting.

You should have strong SystemVerilog, UVM, and constrained-random verification skills, plus debugging and clear communication abilities to interact with stakeholders.

Qualifications

• Experience in developing and maintaining verification components.
• Strong proficiency in SystemVerilog, UVM, and constrained-random verification methodologies.
• Skilled in debugging and identifying root causes of issues.
• Effective communication of technical issues, both verbally and in writing.

Responsibilities

• Design verification plans and develop, maintain UVM testbench components.
• Build UVM testbenches, including writing tests, sequences, checkers, scoreboards, and verification/coverage plans.
• Take ownership of task definition, effort estimation, and progress tracking.
• Contribute to the improvement and evolution of GPU verification methodologies.
• Take ownership of coverage closure and provide verification metric reports.

Skills

SystemVerilog

UVM

Constrained-random verification

Debugging

Communication

Verification components

Tools

Python

TCL

Perl

SystemC

C++

Job description

Imagination Technologies Limited is seeking a hardware verification engineer to design verification plans and build UVM testbenches for cutting-edge PowerVR designs. You will own task definitions, estimates, and progress, while contributing to GPU verification methodology improvements and coverage reporting.

You should have strong SystemVerilog, UVM, and constrained-random verification skills, plus debugging and clear communication abilities to interact with stakeholders.