Senior GPU Verification Engineer – UVM & SystemVerilog

Imagination Technologies Limited; Bagstone; On-site; GBP 60,000 - 90,000; Full time

Job summary

Imagination Technologies Limited is seeking a Senior GPU Verification Engineer to advance hardware verification for cutting-edge PowerVR graphics designs. You will design verification plans, build UVM testbenches, and own coverage metrics while collaborating with the team across multiple verification activities.

You will leverage SystemVerilog, UVM, and constrained-random verification to create robust testbenches, diagnose issues, and report verification status.

Qualifications

• Experience in developing and maintaining verification components.
• Strong proficiency in SystemVerilog, UVM, and constrained-random verification methodologies.
• Skilled in debugging and identifying root causes of issues.
• Effective communication of technical issues, both verbally and in writing.

Responsibilities

• Design verification plans and develop, maintain UVM testbench components.
• Gain a deep understanding of the design and testbench under your responsibility.
• Build UVM testbenches, including writing tests, sequences, checkers, scoreboards, and verification/coverage plans.
• Take ownership of task definition, effort estimation, and progress tracking.
• Contribute to the improvement and evolution of GPU verification methodologies.
• Take ownership of coverage closure and provide verification metric reports.

Skills

SystemVerilog

UVM

Constrained-random verification

Debugging

Communication skills

Python scripting

C++

Tools

Python

TCL

Perl

SystemC

Job description

Imagination Technologies Limited is seeking a Senior GPU Verification Engineer to advance hardware verification for cutting-edge PowerVR graphics designs. You will design verification plans, build UVM testbenches, and own coverage metrics while collaborating with the team across multiple verification activities.

You will leverage SystemVerilog, UVM, and constrained-random verification to create robust testbenches, diagnose issues, and report verification status.