Senior GaN Power IC Design Engineer

Cambridge GaN Devices Ltd

Cambridge

On-site

GBP 90,000 - 120,000

Full time

14 days+
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Benefits offered by this job

Excellent salary
Share options scheme
Pension scheme (6% Company)
Life Assurance (3x Salary)
Private Health Insurance
Medicash cash plan
33 days annual leave

Job summary

Cambridge GaN Devices Ltd seeks an experienced Senior Analog IC Design Engineer to join the R&D team in Cambridge, UK. You will develop GaN power IC solutions, leveraging your expertise in analog IC design, SPICE modelling, and EDA processes.

You will contribute to test development, device modelling, and IP creation while collaborating with a fast-paced startup culture and occasional travel to partners and trials.

Qualifications

  • Master's degree in engineering or science.
  • Comprehensive knowledge and understanding of analog IC design.
  • Experience with schematic capture, analog simulations, chip layout and DRC/LVS/PEX/PLS.
  • Experience with electrical testing and characterisation of analog ICs.
  • Strong project management skills.
  • Proactive, precise and detail-oriented.
  • Excellent communication and presentation abilities.

Responsibilities

  • Design and layout GaN power ICs using EDA tools.
  • Develop tests for GaN Power ICs at wafer and packaged levels.
  • Document, evaluate, and debug chips.
  • Develop SPICE models for GaN ICs.
  • Generate IP and support IP management and patent work.

Skills

Analog IC design
EDA process
Schematic capture
Analog simulations
Chip layout
DRC/LVS/PEX/PLS
Electrical test & characterisation
Project management
Communication skills
Attention to detail

Education

Master's degree in engineering or science

Tools

Cadence Virtuoso
Mentor Calibre

Job description

Cambridge GaN Devices Ltd seeks an experienced Senior Analog IC Design Engineer to join the R&D team in Cambridge, UK. You will develop GaN power IC solutions, leveraging your expertise in analog IC design, SPICE modelling, and EDA processes.

You will contribute to test development, device modelling, and IP creation while collaborating with a fast-paced startup culture and occasional travel to partners and trials.

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