Senior Functional-Safety Verification Lead

Arm Limited; Cambridge; Hybrid; GBP 85,000 - 120,000; Full time

Job summary

Arm seeks a Senior/Staff Safety Verification Engineer to join its engineering team in the Cambridge area. You will verify safety-critical hardware designs and safety mechanisms to meet defined safety requirements and standards.

You will develop verification strategies for functional safety, collaborate with RTL/design and functional-safety teams, and drive safety certification through IP, subsystem, and SoC levels using SystemVerilog/UVM and C/C++.

Qualifications

• Bachelor's or Master’s degree in Electronics, Electrical, or Computer Engineering.
• Strong proficiency in SystemVerilog, Verilog and C/C++.
• Experience with UVM or industry-standard verification methodologies.
• Experience in constrained-random verification environments and reusable components.

Responsibilities

• Collaborate with RTL designers and architects to understand specifications and microarchitecture details.
• Develop and execute verification plans for functional-safety requirements and safety mechanisms at IP, subsystem, and SoC level.
• Develop and maintain verification environments, testbenches, assertions, checkers, and coverage models using SystemVerilog/UVM.
• Debug simulation failures, identify root causes, and work with design engineers to resolve issues.
• Trace safety requirements to verification activities and provide evidence of verification completeness.
• Contribute to safety work products and verification documentation per ISO 26262, IEC 61508, and internal processes.
• Support reviews of safety requirements, safety mechanisms, FMEDA assumptions, fault models, and verification results.
• Contribute to automation and continuous improvement of regression, coverage-analysis, and reporting flows.

Skills

SystemVerilog

Verilog

C/C++

UVM

Python

Education

Bachelor's or Master's in Electronics/Electrical/Computer Engineering

Tools

Sim/Verification toolchains

Job description

Arm seeks a Senior/Staff Safety Verification Engineer to join its engineering team in the Cambridge area. You will verify safety-critical hardware designs and safety mechanisms to meet defined safety requirements and standards.

You will develop verification strategies for functional safety, collaborate with RTL/design and functional-safety teams, and drive safety certification through IP, subsystem, and SoC levels using SystemVerilog/UVM and C/C++.