Senior FPGA Design Engineer

Platform Recruitment; Cambridge; Hybrid; GBP 60,000 - 90,000; Full time

Job summary

Platform Recruitment seeks a Senior FPGA Design Engineer for a hybrid role in Cambridge. You will contribute to high-performance FPGA technology across multiple products, joining a collaborative engineering team in a fast-moving, innovative environment.

You will design reusable modules, write specifications, review code, and help maintain engineering standards. The role focuses on SystemVerilog design, RTL verification, and timing closure, with collaboration across hardware, software and

Qualifications

• Strong SystemVerilog FPGA design experience.
• RTL verification and timing closure skills.
• Familiarity with Python for verification tasks.
• Experience with cocotb for FPGA verification.

Responsibilities

• Design and develop reusable FPGA modules using SystemVerilog for deployment across multiple products.
• Perform RTL verification and support timing closure through constraints, analysis, and design optimisation.
• Write module specifications, review code and documentation, and maintain high engineering standards.
• Collaborate with hardware, software, and mechanical engineers to deliver new products to market.

Skills

SystemVerilog

RTL verification

Python

Tools

Git

SVN

Markdown

Job description

Senior FPGA Design Engineer | Hybrid | Cambridge

Join an innovative technology company developing advanced electronic products used in demanding, high-performance applications. You'll become part of a collaborative engineering team, contributing to the core FPGA technology that powers a range of next-generation products.

Responsibilities

• Design and develop reusable FPGA modules using SystemVerilog for deployment across multiple products.
• Perform RTL verification and support timing closure through constraints, analysis, and design optimisation.
• Write module specifications, review code and documentation, and maintain high engineering standards.
• Collaborate with hardware, software, and mechanical engineers to deliver new products to market.

Essential Experience

• Strong SystemVerilog FPGA design experience.
• RTL verification skills and familiarity with Python.
• Experience writing timing constraints and achieving timing closure.

Desirable Experience

• Experience with cocotb for FPGA verification.
• Familiarity with Linux command line, Git/SVN, and Markdown.

Do you want to work in a high variety, high complexity environment on highly advanced systems?