Senior Digital FPGA Engineer

JR United Kingdom; Chesterfield; Hybrid; GBP 50,000 - 75,000; Full time

Job summary

A leading machine learning company in Chesterfield is seeking a Senior Digital FPGA Engineer. This role involves developing FPGA designs, collaborating with software and ML teams, and contributes to innovative projects. A competitive salary and hybrid working model are offered in this dynamic environment.

Benefits

Competitive salary and benefits

Hybrid working model (3 days on-site, 2 days remote)

Qualifications

• Experience in FPGA design, development, and testing.
• Proficiency in SystemVerilog, VHDL, and/or Verilog.
• Programming skills in C / C++ or Python.

Responsibilities

• Develop FPGA designs using SystemVerilog.
• Collaborate with software and machine learning teams.
• Build low-latency, high-throughput applications.

Skills

FPGA design

SystemVerilog

VHDL

C / C++

Python

Low latency design

Machine learning

Tools

Quartus

Vivado

Job description

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Senior Digital FPGA Engineer, Chesterfield

Client:

Location: Chesterfield, United Kingdom

Job Category: Other

EU work permit required: Yes

Job Views:

1

Posted:

04.06.2025

Expiry Date:

19.07.2025

Job Description:

Senior Digital FPGA Engineer - IP / Machine Learning in Chesterfield

• Based in Chesterfield, UK
• Opportunity to work in a leading Machine Learning / AI technology company
• Competitive salary and benefits, hybrid working (3 days on-site, 2 days remote)

A leading machine learning company specializing in financial technology is seeking experienced Senior Digital Design and FPGA Engineers to join their team. The role offers a dynamic work environment, innovative projects, and excellent benefits.

As a Senior Digital FPGA Engineer, you will develop FPGA designs using SystemVerilog, collaborating with software and machine learning teams to build low-latency, high-throughput applications.

Required skills and experience:

• FPGA design, development, and testing experience
• Proficiency in SystemVerilog, VHDL, and/or Verilog
• Programming skills in C / C++ or Python
• Experience with Quartus and/or Vivado
• Knowledge of low latency, machine learning, or neural network architectures is a plus but not essential

If interested in this hybrid Senior Digital FPGA Engineer role in Chesterfield, please apply with your CV.