Senior Design Verification Engineer

SAMSUNG; Market Drayton; On-site; GBP 60,000 - 80,000; Full time

Job summary

A leading semiconductor company in Market Drayton, United Kingdom is seeking a Senior Design Verification Engineer. This role requires ownership of IP Design Verification, collaboration across teams, and expertise in verification tools such as UVM and SystemVerilog. Ideal candidates should have 7-10 years of experience and a degree in a relevant field. The role emphasizes technical guidance and debugging skills in a diverse, equal opportunity environment.

Qualifications

• 7-10 years of experience required in relevant fields.
• Experience leading IP DV projects independently.

Responsibilities

• Ownership of IP Design Verification (DV).
• Collaborate with cross-functional teams.
• Develop and execute verification activities.

Skills

Verification tools and methodologies

Cross-functional collaboration

Technical guidance and debugging skills

IP Design Verification (DV)

Hybrid testbenches

Domain expertise in CPU

Education

B.Tech/B.E or M.Tech/M.E in relevant fields

Tools

UVM

SystemVerilog

CDV

MDV

Python

Job description

Position Summary

We are seeking a Senior Design Verification Engineer to join our team in Market Drayton, United Kingdom. This role involves working on industry-leading semiconductor solutions across various domains including System LSI, Memory, and Foundry technologies.

Role and Responsibilities

• Ownership of IP Design Verification (DV).
• Collaborate with cross-functional teams across multiple locations.
• Develop and execute verification activities, including test plan creation, building testbenches following standard DV methodology, and developing DV infrastructure such as coverage, regression, and simulation scripts.
• Experience in developing test benches for IP, Subsystems, and SoCs.
• Execute verification of SoC/SS/IP DV with in-depth knowledge.
• Lead IP DV projects independently, providing technical guidance and debugging skills.
• Utilize verification tools and methodologies including UVM, SystemVerilog, CDV, MDV, and DV signoffs.
• Domain expertise in CPU, Cache Coherency, CPU Pipeline, Cache, Branch Prediction, or MMU.
• Experience with hybrid testbenches (SV, C/C++, Python) and CPU vectors/stimulus verification is desirable.
• Exposure to RISC-V Core DV or other core DVs is highly preferred.

Experience: 7-10 Years

Qualifications:

• B.Tech/B.E or M.Tech/M.E in relevant fields.

Additional Information:

Samsung Semiconductor India Research (SSIR) is committed to diversity and equal employment opportunities for all individuals.