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Job summary
A semiconductor start-up in the UK is seeking a Verification Engineer to join their talented team. This role involves working with design teams to define verification requirements for security features, developing verification plans, and executing test plans using UVM methodology. Ideal candidates will possess a Bachelor's or Master's degree in Electrical Engineering, have strong communication skills, and relevant experience in hardware verification. You will thrive in a collaborative environment with good autonomy on tasks.
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Strong understanding of hardware verification methodologies and tools.
Experience with UVM for FPGA/ASIC verification.
Responsibilities
Collaborates with the design team to define verification requirements for security features.
Develops and maintains verification plans, testbenches, and scenarios using UVM methodology.
Executes test plans and verifies correctness of hardware security features.
Skills
Hardware verification methodologies
Communication skills
Collaboration
Education
Bachelor's or Master's degree in Electrical Engineering
Tools
UVM (Universal Verification Methodology)
Job description
A semiconductor start-up in the UK is seeking a Verification Engineer to join their talented team. This role involves working with design teams to define verification requirements for security features, developing verification plans, and executing test plans using UVM methodology. Ideal candidates will possess a Bachelor's or Master's degree in Electrical Engineering, have strong communication skills, and relevant experience in hardware verification. You will thrive in a collaborative environment with good autonomy on tasks.