RTL Front-End Engineer – Mixed Signal Systems

microTECH Global Limited; United Kingdom; Remote; GBP 50,000 - 70,000; Full time

Job summary

A technology company is seeking a highly skilled RTL Front-End Engineer with expertise in Mixed Signal System Design using Verilog and Verilog-AMS. This role involves designing RTL, collaborating with teams, and verifying complex mixed-signal systems. The ideal candidate has strong experience in mixed-signal design and modeling within digital environments.

Qualifications

• Strong experience with Verilog RTL design.
• Hands-on expertise with Verilog-AMS for analog/mixed-signal modeling.
• Proven experience in mixed-signal system design, particularly in front-end RTL.
• Familiarity with mixed-signal simulators.

Responsibilities

• Design and develop RTL for mixed-signal systems using Verilog and Verilog-AMS.
• Collaborate with analog and digital teams to verify mixed-signal IP blocks.
• Perform simulation, verification, and debugging of mixed-signal systems.

Skills

Verilog RTL design

Verilog-AMS modeling

Mixed-signal system design

Simulation and debugging

Signal processing

Strong debugging and analytical skills

Tools

Cadence AMS Designer

Synopsys VCS AMS

Job description

Role: RTL Front-End Engineer – Mixed Signal Systems (Verilog / Verilog-AMS)

Location: remote

Duration: 3 months

Start date: ASAP

About the Role:

We are seeking a highly skilled RTL Front-End Engineer with expertise in Mixed Signal System Design using Verilog and Verilog-AMS. You will be responsible for the specification, design, modelling, and verification of complex mixed-signal systems, working closely with both digital and analog design teams.

This is a critical role at the front end of chip/system design – ideal for someone who excels in modeling analog behaviour within digital environments and bridging the gap between hardware and system-level requirements.

Key Responsibilities:

• Design and develop RTL for mixed-signal systems using Verilog and Verilog-AMS
• Collaborate with analog and digital teams to co-design and verify mixed-signal IP blocks and subsystems
• Develop accurate behavioral and functional models for analog and mixed-signal components
• Perform simulation, verification, and debugging of mixed-signal systems
• Support integration of analog/mixed-signal models into digital verification environments
• Participate in system-level architecture discussions and contribute to design specifications
• Write clear, maintainable, and well-documented code and technical documentation

Key Skills & Experience:

• Strong experience with Verilog RTL design
• Hands-on expertise with Verilog-AMS for analog/mixed-signal modelling
• Proven experience in mixed-signal system design, particularly in front-end RTL and behavioural modeling
• Familiarity with mixed-signal simulators (e.g., Cadence AMS Designer, Synopsys VCS AMS, etc.)
• Solid understanding of analog circuit behaviour (ADC, DAC, PLL, etc.) and how to model it
• Experience with SystemVerilog or UVM (a plus, but not essential)
• Knowledge of signal processing, timing analysis, and mixed-signal verification methodologies
• Strong debugging and analytical skills

Nice to Have:

• Experience with scripting languages (e.g., Python, Tcl)
• Experience working in automotive, communications, or medical sectors
• Knowledge of digital-analog co-simulation environments