Principal Verification Engineer

JR United Kingdom; Bristol; On-site; GBP 50,000 - 70,000; Full time

Job summary

A leading semiconductor company in Bristol is seeking a Principal Verification Engineer to develop and maintain verification environments for complex IPs. This role involves leading the verification strategy and ensuring compliance with quality standards, making it an exciting opportunity for experienced engineers looking to contribute to innovative technology.

Qualifications

• Minimum 5 years of IP-level verification experience using SystemVerilog UVM.
• Strong understanding of UVM methodology and verification metrics.
• Excellent communication skills and a detail-focused approach.

Responsibilities

• Develop and maintain SystemVerilog UVM testbenches for complex IPs.
• Lead the creation of new UVM verification components.
• Debug test failures and define functional coverage models.

Skills

SystemVerilog UVM

Verification Metrics

Communication Skills

Tools

EDA Tools

Scripting Languages

Job description

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Principal Verification Engineer, bristol

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Client:

Platform Recruitment

Location:

bristol, United Kingdom

Job Category:

Other

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EU work permit required:

Yes

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Job Views:

2

Posted:

23.05.2025

Expiry Date:

07.07.2025

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Job Description:

My client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap.

They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join.

Principal Verification Engineer

Responsibilities:

• Develop and maintain SystemVerilog UVM testbenches for complex IPs.
• Lead the creation of new UVM verification components and contribute to testbench architecture
• Debug test failures and define functional coverage models to ensure sign-off quality.
• Work closely with designers and contribute to verification strategy during design and concept phases.
• Improve verification efficiency and ensure compliance with functional safety and quality standards.

Requirements:

• Minimum 5 years of IP-level verification experience using SystemVerilog UVM.
• Strong understanding of UVM methodology, SVAs, and verification metrics.
• Ability to interpret complex design specifications and create robust verification environments.
• Proficiency in industry-standard EDA tools and scripting languages.
• Excellent communication skills and a methodical, detail-focused approach.