Physical Design Engineer - Foundry Team

SAMSUNG; Market Drayton; On-site; GBP 60,000 - 80,000; Full time

Job summary

A leading semiconductor company is seeking a Physical Design Engineer for its Foundry Team in Market Drayton. The role involves physical implementation, timing analysis, and design closure for complex SOCs. Ideal candidates will have over 5 years of experience in SOC design and a relevant degree. Proficiency in industry-standard EDA tools and scripting is essential. This position offers an opportunity to work on cutting-edge technologies.

Qualifications

• Minimum 5+ years in physical design of SOCs.
• Experience with large SOC designs (>20M gates).
• Ability to debug LVS/DRC issues.

Responsibilities

• Perform physical design and timing closure for complex SOC blocks.
• Engage in top-level floor planning.
• Optimize for power, performance, and area trade-offs.
• Utilize industry-standard EDA tools.
• Develop and maintain automation scripts.
• Conduct SDC cleanup and synthesis optimization.
• Address deep sub-micron process node issues.
• Participate in hierarchical design methodologies.
• Contribute to SOC tape-outs.

Skills

Physical design

Timing closure

Power optimization

Perl/Tcl scripting

SOC design

EDA tools

Education

B.Tech/B.E or M.Tech/M.E in relevant field

Tools

ICC

DC

PT

VSLP

Redhawk

Calibre

Formality

Job description

Position: Physical Design Engineer - Foundry Team, Market Drayton

Client:

SAMSUNG

Location:

Market Drayton, United Kingdom

Job Category:

Other

EU work permit required:

Yes

Job Reference:

d3e79e2c8732

Job Views:

27

Posted:

12.08.2025

Expiry Date:

26.09.2025

Job Description:

Position Summary

Samsung Semiconductor is seeking a Physical Design Engineer to join the Foundry Team in Market Drayton. The role involves working on complex SOC physical implementation, including synthesis, place and route, timing analysis, and physical signoff of next-generation SOCs for mobile applications, connectivity, and other advanced technologies.

Roles and Responsibilities

• Perform physical design and timing closure for complex SOC blocks and full-chip designs.
• Engage in top-level floor planning, including partitioning, pin placement, and signal planning.
• Optimize for power, performance, and area trade-offs.
• Utilize industry-standard EDA tools such as ICC, DC, PT, VSLP, Redhawk, Calibre, and Formality.
• Develop and maintain scripts in Perl/Tcl for automation.
• Work on large SOC designs (>20M gates) with high frequency requirements.
• Conduct SDC cleanup, synthesis optimization, low power checks, and logic equivalence checks.
• Address issues related to deep sub-micron process nodes (8nm/5nm).
• Manage multiple voltage and clock domains, ESD strategies, and package interactions.
• Participate in hierarchical and top-down design methodologies, including timing and physical convergence.
• Debug LVS/DRC issues during verification.
• Contribute to successful SOC tape-outs.

Experience: Minimum 5+ years in physical design of SOCs.

Qualifications: B.Tech/B.E or M.Tech/M.E in relevant field.

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