Physical Design Engineer - Foundry Team

SAMSUNG; Market Drayton; On-site; GBP 55,000 - 75,000; Full time

Job summary

Une entreprise leader dans le domaine des semi-conducteurs cherche à recruter un ingénieur design physique pour son équipe de Market Drayton. Le poste implique la conception de SOCs complexes, avec une forte responsabilité sur le timing et l'optimisation de puissance. Vous travaillerez avec des outils industriels pour réaliser des conceptions à la pointe de la technologie et participerez à des projets innovants dans un environnement dynamique.

Qualifications

• Minimum 5 ans d'expérience en design physique.
• Expérience avec des designs SOC de plus de 20M de portes.
• Connaissance des méthodologies de conception hiérarchiques et de la vérification physique.

Responsibilities

• Concevoir et mettre en œuvre le design physique pour des SOCs complexes.
• Optimiser le timing, la puissance, et les échanges de zone pour un PPA optimal.
• Développer et maintenir des scripts pour automatiser les flux de conception.

Skills

Design de circuits intégrés

Vérification physique

Automatisation des flux de conception

Travail avec des designs SOC complexes

Education

B.Tech/B.E ou M.Tech/M.E

Tools

ICC

DC

PT

Redhawk

Calibre

Formality

Job description

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Physical Design Engineer - Foundry Team, Market Drayton

Client: SAMSUNG

Location: Market Drayton, United Kingdom

Job Category: Other

EU work permit required: Yes

Job Reference: d3e79e2c8732

Job Views: 5

Posted: 29.06.2025

Expiry Date: 13.08.2025

Job Description:

Position Summary

Samsung Semiconductor is a leading provider of industry-leading semiconductor solutions, enabling innovative growth in segments such as System LSI, Memory, and Foundry. Our engineers work on cutting-edge technologies including Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/6G, Neural processors, Serial Interfaces, Multimedia IPs, and more.

As one of the largest R&D centers outside Korea, we pride ourselves on working on advanced technologies. Our engineers collaborate across diverse domains, projects, and countries, conducting research in emerging technology areas. Innovation and creativity are highly valued as we aim to deliver high reliability, high performance, and value-added services to support Samsung Electronics' world-class products.

Roles and Responsibilities:

• Design and implement physical design and timing closure for complex SOCs, including mobile application processors, modem sub-systems, and connectivity chips, using synthesis, place and route, STA, and physical signoff tools.
• Perform top-level floor planning, including partition shaping, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning.
• Optimize for timing, power, and area trade-offs to achieve optimal PPA.
• Utilize industry-standard tools such as ICC, DC, PT, VSLP, Redhawk, Calibre, and Formality effectively.
• Develop and maintain scripts using Perl/Tcl to automate design flows.
• Work with large SOC designs (>20M gates) operating at frequencies above 1GHz.
• Perform block-level and full-chip SDC cleanup, synthesis optimization, low power checking, and logic equivalence checking.
• Address challenges related to deep sub-micron designs (8nm/5nm), including manufacturability, power, and signal integrity issues.
• Manage SOC issues such as multiple voltage and clock domains, ESD strategies, mixed-signal integration, and package interactions.
• Implement hierarchical and top-down design methodologies, including budgeting, timing, and physical convergence.
• Debug LVS/DRC issues at chip and block levels using physical design verification methods.
• Participate in recent successful SOC tape-outs.

Experience: 5+ years in physical design and implementation.

Qualifications:

• B.Tech/B.E or M.Tech/M.E degree.

Disclaimer:

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd, is committed to diversity and equal employment opportunity, regardless of religion, gender, age, marital status, gender identity, veteran status, genetic information, disability, or other protected characteristics.

Skills and Qualifications:

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