Physical Design Engineer

ZipRecruiter; Cambridge; Hybrid; GBP 50,000 - 70,000; Full time

Job summary

A leading technology company based in Cambridge is seeking an experienced engineer for a contract role focused on RTL development of advanced GPU technology. The role involves working within a dynamic project team, managing the implementation flow from RTL to STA, optimizing PPA, and collaborating with various teams and tool vendors to meet project goals. This position offers an exciting opportunity to leverage your skills in a cutting-edge environment with a hybrid work model.

Qualifications

• Experience with Cadence tools (Genus, Innovus, Tempus).
• Knowledge of PnR flow stages and low power design techniques.
• Understanding of scripting using TCL, Python, Perl.

Responsibilities

• Develop the next Mali GPU through full PnR flow.
• Provide feedback to RTL designers and log details in Jira.
• Collaborate with team members and enhance implementation techniques.

Skills

RTL development

PPA optimization

Collaboration

Problem-solving

Tools

Cadence tools

Synopsys tools

Job description

Job Description

Your new company
In this role, your directive will be to influence RTL development for best-in-class PPA whilst innovating, crafting, and deploying the latest implementation techniques on live projects pushing the boundaries of power, area, and frequency.

Your new role
Location - Cambridge (Hybrid - 2 days per week working from the office)
Contract duration - 4 to 6 months

You will work within a project team of 6 people to develop the next Mali GPU, handling multiple build blocks (~1.5 million instances each) within a hierarchical GPU through the full PnR flow from RTL to STA for multiple milestone release cycles. Responsibilities include providing detailed feedback to RTL designers, logging details in Jira, and communicating via email/IM to push PPA and achieve project goals within the timeline. Collaboration with team members and sharing information across project teams is essential due to hierarchical dependencies.

You will be responsible for all stages from RTL to STA, including logical equivalence checking (LEC) and conformal low power (CLP) checking, as well as constraint and UPF development and debugging.

• Physical implementation of Arm graphics processors using the entire implementation flow from RTL through place and route to STA.
• Providing RTL feedback to designers via Jira to improve PPA and remove implementation bottlenecks.
• Collaborating with EDA vendors to resolve tool issues and enhance PPA.
• Planning and scheduling your work in line with project goals and needs.

What you'll need to succeed

• Experience with Cadence tools: Genus, Innovus, Tempus, QRC, and Conformal.
• Knowledge of PnR flow stages: Synthesis, LEC, CLP, Floorplanning, Placement, CTS, Post-CTS, Routing, STA.
• Familiarity with Synopsys tools: Fusion Compiler, Formality.
• Experience with synthesis and LEC.
• Knowledge of low power design techniques (power gating, DVFS, etc.).
• Understanding of building flows and methodologies using scripting languages such as TCL, Python, Perl to support project development.

What you need to do now
If you're interested in this role, click 'apply now' to submit an up-to-date CV or contact us directly.

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