Physical Design

Chipright; United Kingdom; Remote; GBP 60,000 - 80,000; Full time

Job summary

A leading technology firm in the United Kingdom is seeking Physical Design Engineers specializing in digital IC design flow, particularly in TSMC 7nm process. Candidates should have experience with block-level timing closure and physical verification. The role involves responsibilities in clock constraints, floorplanning, and implementation of design views. Interested candidates can reach out via email for further information.

Qualifications

• Experience of advanced process nodes (16nm and lower) is highly desired.
• Proficiency in full digital IC design flow crucial.

Responsibilities

• Create clock constraints and perform block-level clock tree synthesis.
• Ownership of block-level timing closure activities.
• Floorplanning of the blocks.
• Complete place and route of the blocks.
• Physical verification of the blocks.
• Signoff STA of the blocks.
• Creation of all necessary design views for integration into top-level.
• Implementation of top-level signoff-driven ECOs.
• Contribute to top-level design closure and signoff.
• Perform and ensure clean signoff checks for timing and physical verification.
• Organize regular review of tasks in progress.
• Complete all documentation associated with the above tasks.

Skills

Physical verification

Timing closure

Place and Route

Clock tree synthesis

Block-level implementation

Tools

Cadence Innovus

IC Compiler II

Job description

Chipright is looking for Physical Design Engineers who are experts in the full digital IC design flow and specifically in floorplanning, the complete Place and Route flow, Signoff Static Timing Analysis, Timing closure activities, and physical verification.

The scope of work includes the physical implementation of blocks in TSMC 7nm process, with the following responsibilities:

• Create clock constraints and perform block-level clock tree synthesis
• Ownership of block-level timing closure activities
• Floorplanning of the blocks
• Complete place and route of the blocks
• Physical verification of the blocks
• Signoff STA of the blocks
• Creation of all necessary design views for integration into top-level
• Implementation of top-level signoff-driven ECOs
• Contribute to top-level design closure and signoff
• Perform and ensure clean signoff checks for timing, physical verification, multi-voltage, formal, and IRDROP for all agreed blocks
• Organize regular review of tasks in progress or completed
• Complete all documentation associated with the above tasks

Requirements:

• Experience of advanced process nodes (16nm and lower) is highly desired
• Experience of Cadence Innovus or IC Compiler II is highly desired

Please contact [e-mail] for more details.

Equal Employment Opportunity statement: Chipright is an equal opportunities employer and welcomes applications from all qualified candidates.