Kernel Engineer

microTECH Global LTD; United Kingdom; Remote; GBP 110,000 - 150,000; Full time

Job summary

microTECH Global Limited seeks a Principal Kernel Engineer in Cambridge, UK to optimize memory management, scheduling, and synchronization in a production-grade kernel environment.

You will work with big.LITTLE/DynamIQ topologies, ARM64 barriers, and energy-aware scheduling, delivering patches backed by latency and power data.

Qualifications

• 10+ years of OS kernel development in C with patches shipped to production systems.
• Expert MM internals: physical/virtual memory, buddy/slab, reclaim, compaction, page tables, TLB.
• Deep scheduler knowledge: CFS/EEVDF, load balancing, preemption, real-time classes, energy-aware scheduling.
• Mastery of kernel synchronization: locking primitives, RCU, lock-free techniques, the ARM64 memory model and barrier semantics.
• Proven kernel performance-analysis skills: PMU counters, ftrace/perf, eBPF, latency analysis.
• Strong ARM64 architecture grounding: exception levels, cache hierarchy and maintenance, TLBs, memory ordering.

Responsibilities

• Optimize memory management internals: buddy allocator, slab/SLUB, page reclaim and LRU/MGLRU, memory defragmentation and THP.
• Drive scheduler performance: run-queue and load-balancing, energy-aware scheduling, wakeup latency, task placement on big.LITTLE/DynamIQ.
• Improve synchronization primitives and lock-heavy paths: futex, mutexes, rwsems, spinlocks, RCU, barrier semantics on ARM64.
• Analyze IPC and syscall paths: context-switch cost, shared memory, vDSO, interrupt handling.
• Identify bottlenecks on flagship workloads using PMU counters, ftrace/perf, eBPF, and power measurements.
• Land production-quality kernel patches from hypothesis through benchmarking to ship with measured latency/energy impact.

Skills

OS kernel development

C programming

Linux kernel patches

MM internals

ARM64 memory model

RCU & locking

Performance analysis

Scheduler internals

Job description

Job Title: Principal Kernel Engineer

Location: Cambridge, UK

Type: Permanent

Our client are an international semiconductor and consumer electronics company.

The Role

Optimize memory management internals: buddy allocator, slab/SLUB, page reclaim and LRU/MGLRU, memory compaction and defragmentation, transparent huge pages, page-fault and TLB-shootdown paths, copy-on-write behaviour

Drive scheduler performance: run-queue and load-balancing behaviour, energy-aware scheduling, wakeup latency, task placement on heterogeneous (big.LITTLE/DynamIQ) topologies, cpufreq/cpuidle governor interaction

Optimize synchronization primitives and lock-heavy paths: futex fast/slow paths, mutexes and rwsems, spinlocks/qspinlocks, RCU, seqlocks, per-CPU data, memory ordering and barriers on ARM64

Analyse and improve IPC and syscall paths: context-switch cost, binder-style IPC, shared memory, vDSO, interrupt/softirq handling

Identify bottlenecks on flagship mobile workloads (gaming, day-of-use, camera, AI inference) using PMU counters, ftrace/perf, eBPF, lockdep/lockstat, and power measurement with mA/mAh attribution

Land production-quality kernel patches from hypothesis through benchmarking to ship, with measured latency and energy impact

Must-Haves

10+ years of OS kernel development in C (Linux or comparable), with patches shipped to production systems at scale

Expert-level understanding of MM internals: physical/virtual memory management, buddy and slab allocation, reclaim, compaction, page tables, TLB management

Deep scheduler knowledge: CFS/EEVDF internals, load balancing, preemption, real-time classes, energy-aware scheduling

Mastery of kernel synchronization: locking primitives, RCU, lock-free techniques, the ARM64 memory model and barrier semantics

Proven kernel performance-analysis skills: PMU counters, ftrace/perf, eBPF, lock contention and latency analysis

Strong ARM64 architecture grounding: exception levels, cache hierarchy and maintenance, TLBs, memory ordering