IC Verification Engineer

Raspberry Pi Foundation; Cambridge; On-site; GBP 60,000 - 90,000; Full time

Benefits offered by this job

Competitive salary

Employer pension 8%

Life assurance 4× base salary

Income protection 75%

Private medical insurance

EV salary sacrifice scheme

Job summary

Raspberry Pi Foundation is seeking an IC Verification engineer to join our ASIC team in Cambridge. You will own IP and chip‑level verification planning and execution, coordinating with design to ensure robust silicon from specs through to sign‑off.

The role involves building test benches, debugging complex failures, and collaborating across teams to deliver next‑generation Raspberry Pi silicon.

Qualifications

• Experience in IC verification and silicon flow from spec to sign-off.
• Ability to analyze and debug non-trivial test failures.
• Strong communication and teamwork capabilities.

Responsibilities

• Own IP and chip-level verification planning and execution.
• Collaborate with design team to produce verification plans and testbenches.

Skills

Self-starter

Design flow understanding

Debugging test failures

Interpersonal skills

Communication skills

Tools

Cadence tool flow

Jasper

Gate-level simulation

Bash

TCL

Make

YAML

Job description

Overview

Raspberry Pi is seeking an IC Verification engineer to join our expanding ASIC team to help deliver our next-generation products. We have been building our own silicon at Raspberry Pi for some years now, starting with the RP2040 microcontroller in 2021, and following with the RP1 southbridge chip for the main Raspberry Pi platform on Raspberry Pi 5. Our second-generation microcontroller, RP2350, was released in 2024. The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and qualification. With a small team, we get involved in all aspects of getting successful products into production.

Responsibilities

As a Verification Engineer, you will take ownership for IP and chip level verification planning and execution, and will be constantly interacting with the design team, composing detailed verification plans and creating test benches from scratch or using shared verification components.

Key requirements

• A self-starter, able to identify, plan, and execute a wide range of verification tasks as required.
• Able to demonstrate a good understanding in all aspects of the design flow from synthesis through to silicon sign-off.
• Able to analyse and debug non-trivial test failures.
• Able to demonstrate excellent interpersonal and communication skills.

The following would also be useful

• SoC verification concepts: memory caches, DMA, security architecture (TrustZone or equivalent).
• Formal experience with Jasper or similar tools.
• Experience of Cadence simulation tool flow including gate-level simulation.
• Scripting languages: Bash, TCL, Make, YAML, etc.

Location & Role Details

The role is based in Cambridge with an expectation of full-time office attendance.

Benefits

• Competitive salary based on level of experience
• Employer pension contributions of 8% when the employee contributes 4% of their gross salary into the salary sacrifice scheme
• Life assurance of 4 × base salary
• Income protection of 75% of base salary in the event of critical illness, commencing after 13 weeks of long-term illness or absence from work
• Private medical insurance (medical history disregarded)
• Access to our electric vehicle salary sacrifice scheme, subject to eligibility