FY27 Intern - Formal Verification Engineering Internship - 6 months, Cambridge

Qualcomm; Cambridge; On-site; GBP 17,000 - 25,000; Part time

Job summary

Qualcomm Technologies International Ltd in Cambridge is seeking an Intern for the Interns Group to join a world-class CPU design team. You will develop formal verification skills and contribute to end-to-end verification from architecture to micro-architecture.

Work with the design team to understand design intent, define verification plans, and build end-to-end sign-off environments for CPU components. Applicants are pursuing a Bachelor's/Master’s in STEM or a PhD.

Qualifications

• Pursuing bachelor’s or master’s degree with courses on computer architecture and Verilog HDL design or formal methods.
• PhD candidates in Mathematics, Science, Engineering, or related field encouraged.
• Equivalent experience considered if duties can be demonstrated.

Responsibilities

• Work with design team to understand design intent and bring up verification plans and schedules with an eye towards the end-to-end formalisation of the refinement from architecture to micro-architecture
• Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components

Education

Bachelor’s or Master’s degree in Mathematics, Science, Engineering, or related field

PhD in Mathematics, Science, Engineering, or related field

Job description

Company: Qualcomm Technologies International Ltd

Job Area: Interns Group, Interns Group > Interim Intern

General Summary

Are you interested in working with a world-class CPU design team? The Qualcomm CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Develop your formal verification skills to their fullest on some of the complex designs ever attempted.

Roles and Responsibilities

• Work with design team to understand design intent and bring up verification plans and schedules with an eye towards the end-to-end formalisation of the refinement from architecture to micro-architecture
• Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components

Minimum Qualifications

• Currently pursuing Bachelor’s or Master’s degree in Mathematics, Science, Engineering, or related field with relevant courses on computer architecture and Verilog HDL design or formal methods.
• OR
• Currently pursuing PhD in Mathematics, Science, Engineering, or related field.
• *References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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