FPGA Developer- Leading Global Market Marker | London, UK

Oxford Knight; London; On-site; GBP 60,000 - 80,000; Full time

Job summary

A leading market maker is seeking FPGA Developers to join their dynamic engineering team. This role involves designing and implementing FPGA solutions for ultra-low-latency trading systems, working closely with traders and technologists to enhance algorithmic trading capabilities.

Benefits

Collaborative environment

Competitive compensation

Flexible working arrangements

Regular social events

Qualifications

• Minimum 2 years' experience in FPGA design lifecycle.
• Experience working in a Linux environment.

Responsibilities

• Design and deploy proprietary hardware trading systems.
• Collaborate with technologists and traders.

Skills

Problem Solving

Analytical Skills

Education

Bachelor's degree in Computer Engineering

Bachelor's degree in Computer Science

Tools

Verilog

SystemVerilog

Python

C++

Job description

Summary

FPGA Developers are sought for a leading market maker to join their fast-paced, dynamic engineering team. This role offers an opportunity to work on the research, design, and implementation of FPGA solutions for ultra-low-latency trading systems.

Your main focus will be designing and deploying proprietary hardware trading systems from concept to production. You will collaborate with technologists and traders to design ultra-low latency, high-throughput, FPGA-based custom financial trading systems to accelerate algorithmic trade signal generation and order execution.

The FPGA team is small, highly experienced, and continuously seeking ways to improve productivity. They are looking for strong, analytical problem-solvers to help build the next generation of cutting-edge, ultra-low-latency hardware solutions.

Requirements

1. Minimum 2 years' experience in the full ASIC or FPGA design lifecycle, including hardware architecture, RTL coding, simulation, verification, system integration, and testing.
2. Experience working with Verilog, SystemVerilog, and either Python or C++.
3. Strong knowledge of FPGA design flow or physical design.
4. Ability to work in a Linux environment.
5. Bachelor's degree in Computer Engineering, Computer Science, or a related field.

Financial experience is not required.

Rewards and Incentives

• Collaborative environment between teams, unlike siloed structures in other firms.
• Competitive compensation with a truly flat structure; your input is valued and rewarded.
• Opportunity to work with the latest technologies on complex problems.
• Flexible working arrangements and regular social events.

While all applications are carefully reviewed, due to the high volume, we may not respond to unsuccessful applicants.

Contact

If you believe you are suitable for this role or want more information, please contact:

Jack Peck

Email: [e-mail]

Phone: [phone]

LinkedIn: linkedin.com/in/jack-peck-448a70131