FPGA Design Engineer

Oriole Networks; London; On-site; GBP 40,000 - 65,000; Full time

Job summary

An innovative technology company is seeking FPGA Engineers to develop advanced network interface cards and control solutions. The role involves defining microarchitecture, implementing designs, and conducting thorough testing using SystemVerilog. Ideal candidates will possess hands-on FPGA experience, expertise in tools like Quartus and Vivado, and a degree in electronics engineering or a related field.

Qualifications

• Hands-on experience of FPGA design, ideally in a product development setting.
• Excellent skills in SystemVerilog/Verilog/VHDL.
• Strong knowledge of FPGA tool flows.

Responsibilities

• Microarchitecture definition in collaboration with the broader team.
• RTL Implementation, synthesis, timing closure.
• Delivering and validating FPGA-based lab setups for customer trials.

Skills

FPGA Design

SystemVerilog

Verilog/VHDL

Scripting and Automation

Clock Domain Crossing Techniques

Education

Bachelor or Master degree in Electronics Engineering

Tools

Quartus

Vivado

Vitis

Job description

We are looking for FPGA Engineers to develop high-speed network interface card and network control solutions. These engineers will be part of the team building solutions to connect GPU systems to our innovative photonic network.

Responsibilities will include microarchitecture definition, implementation, and testing, as well as interfacing with software.

Responsibilities:

• Microarchitecture definition in collaboration with the broader team.

• RTL Implementation, synthesis, timing closure.

• Unit verification planning and simulation testing using SystemVerilog.

• Delivering and validating FPGA-based lab setups for customer trials.

• Preparing detailed technical documentation and presentations to stakeholders.
  
  
  

Skills & Experience:

• Hands-on experience of FPGA design, ideally in a product development setting.

• Excellent skills in SystemVerilog/Verilog/VHDL.

• Strong knowledge of FPGA tool flows (synthesis, partitioning, place & route, timing analysis).

• Familiarity with SystemVerilog for verification, including constrained random verification.

• Comprehensive understanding of clock domain crossing techniques.

• Scripting and automation, such as TCL and Python.

• Experience using Quartus/Vivado/Vitis.

• Experience using PCIe, DDR4, high-speed transceivers and Ethernet is desirable.

• Experience with embedded systems, including soft processors (Nios/Microblaze/RISC V) and SoC programming.

• Bachelor or Master degree in electronics engineering, physics, or other relevant fields or experience within the industry.