Experienced Ic Design Engineer

Raspberry Pi Ltd; Cambridge; On-site; AUD 172,000 - 248,000; Full time

Benefits offered by this job

Employer pension contributions 8%

Life assurance 4 × base salary

Income protection 75% of base salary

Private medical insurance

EV salary sacrifice scheme

Job summary

Raspberry Pi Ltd is seeking an experienced IC Design engineer to lead front-end tasks through specification, design, verification and implementation. You will own IP integration, verification planning and work closely with software teams, supporting FPGA platforms for rapid development and addressing power and timing concerns.

Based in Cambridge with full-time office attendance, the role demands a deep understanding of SoC/MCU design, RTL, UVM and related tooling, plus strong communication and

Qualifications

• 10+ years in SoC or MCU architecture with at least one tape-out.
• Deep understanding of microcontroller and processor design, RT behavior and peripherals.
• Knowledge of interconnect, memory controllers, and security architecture.
• Fluent in RTL (SystemVerilog) and verification methodologies (UVM, formal).
• Experience communicating trade-offs under cost and schedule pressure.
• Ability to work close to software and understand SDK implications.
• Strong communication, initiative, and schedule discipline.
• Familiar with scripting languages (Bash, Python, Tcl).

Responsibilities

• Own front-end tasks from specification to design, verification and implementation.
• Design, IP integration, verification planning and execution.
• Configure IP and systems and collaborate with software teams.
• Support FPGA platforms for fast software development and verification.
• Assist implementation team with power and timing issues.

Skills

SoC architecture

SystemVerilog

UVM verification

ASIC/FPGA design

embedded C programming

power/timing analysis

Scripting (Bash, Python, Tcl)

interconnect protocols (AXI/AHB/APB)

debug/troubleshooting

Tools

Cadence simulation tool flow

Emulation/FPGA

DFT architectures/tools

Power analysis tools

Scripting tools

Job description

Raspberry Pi is seeking an experienced IC Design engineer to join our expanding ASIC team to help deliver our next‑generation products. We have been building our own silicon at Raspberry Pi for some years now, starting with the RP2040 microcontroller in 2021, and following with the RP1 southbridge chip for the main Raspberry Pi platform on Raspberry Pi 5. Our second‑generation microcontroller, RP2350, was released in 2024. The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and qualification. With a small team, we get involved in all aspects of getting successful products into production.

As an experienced design engineer, you will take ownership of front‑end tasks from specification to design, verification, and implementation with support from specialists in other teams. You will be capable of both working autonomously and also dynamically with other members of the ASIC team. Your responsibilities will include:

• Design, IP integration, verification planning and execution
• Specifying and/or configuring IP and systems
• Working closely with the software team
• Supporting FPGA platforms for fast software development and verification
• Assisting the implementation team with power and timing issues

Key requirements

• A good level of experience (typically 10+ years) in SoC or MCU architecture, with at least one tape‑out where you held architectural ownership of a chip or non‑trivial subsystem.
• Deep understanding of modern microcontroller and processor design, including real‑time behaviour, deterministic interrupt handling, low‑power modes, flash/SRAM hierarchies, and common peripherals (e.g. SPI, I²C, UART, USB, PIO‑style fabrics, ADC/DAC, timers).
• Equally strong grasp of broader SoC concepts: coherent and non‑coherent interconnect, AXI/AHB/APB, cache hierarchies, DMA, memory controllers, security architecture (TrustZone or equivalent), and how an OS‑class subsystem coexists with real‑time domains on the same die.
• Fluent in the implementation reality of chips — RTL (SystemVerilog), verification methodology (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints. You do not need to be a specialist in each, but you need to be credible across all of them.
• Track record of making good engineering trade‑offs under real cost, schedule, and PPA pressure, and communicating them clearly to both engineers and non‑engineers.
• Comfortable working close to software: you have written non‑trivial embedded C, understand toolchain and SDK implications of architectural choices, and care about what shipping the chip feels like for the developer using it.
• Ability to communicate complex ideas, design goals, and status effectively both verbally and through documentation.
• Strong drive and ability to work to a schedule.
• Familiarity with scripting languages (Bash, Python, Tcl, etc)

The following would also be useful:

• Experience of Cadence simulation tool flow.
• Experience with ASIC/FPGA synthesis and implementation, DFT architecture and insertion, software development, and scripting.

The role is based in Cambridge with an expectation of full‑time office attendance.

• Competitive salary based on level of experience
• Employer pension contributions of 8% when the employee contributes 4% of their gross salary into the salary sacrifice scheme
• Life assurance of 4 × base salary
• Income protection of 75% of base salary in the event of critical illness, commencing after 13 weeks of long‑term illness or absence from work
• Private medical insurance (medical history disregarded)
• Access to our electric vehicle salary sacrifice scheme, subject to eligibility