Electronic FPGA Engineer HUBER+SUHNER Polatis

Cambridge Science Park; United Kingdom; Remote; GBP 65,000 - 90,000; Full time

Job summary

Cambridge Science Park is seeking an experienced FPGA Engineer to design and verify FPGA logic using VHDL for Artix-7 devices, targeting reliable FSM control of hardware interfaces.

You will develop and test low-level drivers (I2C/SPI/UART), write test benches, and perform lab bring-up with timing analysis, SRL, and CDC considerations.

Qualifications

• Degree or equivalent experience in Electronic/Electrical or Computer Engineering.
• Strong hands-on VHDL for FPGA design and verification.
• Proven experience with Xilinx Artix-7 and Vivado toolchain.
• Ability to design deterministic FSMs for control/driver logic.
• Experience implementing low-level embedded interfaces: I2C, SPI, UART.
• Experience writing self-checking test benches and performing simulation.
• Hardware bring-up, lab testing, timing/constraint validation.
• Familiarity with SVN and basic scripting to automate flows.
• Typically 3+ years FPGA development in product/R&D environments.

Responsibilities

• Design & implement FPGA logic in VHDL for Artix-7 using Vivado.
• Develop finite state machines to sequence hardware interfaces and protocols.
• Create low-level driver logic for I2C and SPI with initialization and error handling.
• Write and maintain test benches; perform functional and timing simulations.
• Hardware bring-up, lab testing, measurements, and iterative debugging.
• Manage constraints (XDC), clocking, resets, and timing closure.
• Contribute to requirements, architecture, module specs, and DFT/DFM.
• Maintain SVN-based configuration and traceability to requirements.
• Produce design docs, registers/interfaces, test procedures, and release notes.
• Participate in design/code reviews and support system integration.

Skills

VHDL

FPGA design

FSM design

I2C

SPI

UART (desirable)

Education

Electronic/Electrical Engineering or Computer Engineering degree

Tools

Vivado

Xilinx Artix-7

SVN

Tcl/Python scripting

Job description

Your tasks

Design & implement FPGA logic in VHDL for Xilinx Artix-7 devices using Vivado, adhering to coding standards and design reviews.

Develop finite state machines to control and sequence hardware interfaces and protocols reliably.

Create low-level driver logic for I²C, SPI (and other simple serial interfaces), including initialisation, transaction handling, and error conditions.

Write and maintain test benches (self-checking where practical), conduct functional and timing simulations, and document verification results.

Perform hardware bring-up and validation, including lab testing, measurements, and iterative debug; collaborate on board-level constraints and interface timing.

Manage constraints (XDC), clocking, resets, and CDC analysis; achieve timing closure and generate production-ready bitstreams.

Contribute to requirements capture, architecture design, module specifications, and DFT/DFM considerations for FPGA-based systems.

Maintain configuration management (SVN), branching/release processes, and traceability to requirements.

Produce and maintain technical documentation: design descriptions, registers/interfaces, test procedures, and change logs.

Participate in design and code reviews, support system integration, and assist production/field teams with issue triage.

Support continuous improvement of FPGA design flows, test coverage, and automation (e.g., Tcl/Python scripts).

Your profile

Degree or equivalent experience in Electronic/Electrical Engineering, Computer Engineering, or related discipline.

Strong hands-on experience with VHDL for FPGA design and verification.

Proven experience targeting Xilinx Artix-7 families; confident using Vivado (project setup, constraints, synthesis, place & route, timing closure, bitstream generation).

Ability to design deterministic finite state machines (FSMs) for control/driver logic.

Experience implementing and validating low-level embedded interfaces: I²C, SPI, UART (desirable), including bus arbitration, timing, and protocol edge cases.

Competence in writing self-checking test benches and performing simulation (e.g., using Vivado simulator).

Experience testing on hardware: bringing up boards, using logic analysers/oscilloscopes, debugging timing/constraint issues, and validating firmware in-system.

Understanding of timing constraints (XDC), clock domain crossing (CDC), metastability, resets, and synchronous design best practices.

Familiarity with version control (e.g., SVN).

Optional but beneficial: knowledge of PCB-level considerations, signal integrity, and simple scripting (Tcl/Python) to automate flows.

Typically 3+ years in FPGA development within a product or R&D environment (or demonstrable equivalent).

Track record of delivering FPGA features/modules from requirements through to validated hardware.

Experience collaborating with electronics engineers and embedded software engineers for system integration.

Clear communicator with strong documentation habits (design specs, interface descriptions, test plans, release notes).

Methodical problem-solver with attention to detail; able to work independently and in cross-functional teams.

Ownership mindset with a focus on reliability, maintainability, and testability.