Senior FPGA Engineer

Platform Recruitment; England; Hybrid; GBP 80,000 - 100,000; Full time

Job summary

An innovative firm is seeking a Senior FPGA Engineer to contribute to groundbreaking projects in high-speed internet and smart city solutions. This role involves engaging in the complete development cycle, collaborating with diverse teams, and ensuring the technical integrity of design documentation. The ideal candidate will possess a strong background in FPGA fundamentals and telecommunications, along with proficiency in Verilog/System Verilog. With a competitive salary and attractive benefits, this opportunity offers a chance to make a significant impact in the tech landscape. If you're passionate about advancing technology and eager to take on new challenges, this position is perfect for you.

Benefits

Healthcare

Pension scheme

25 days holiday + bank holidays

Qualifications

• In-depth knowledge of FPGA design and implementation.
• Experience in telecommunications and high-speed interface design.

Responsibilities

• Involvement in the full development cycle from design to testing.
• Collaborate with a multi-disciplinary team for project success.

Skills

FPGA fundamentals

Verilog/System Verilog

RTL-level design

Telecommunications experience

4G or 5G standards knowledge

Tools

Python

Shell

Perl

PCIe

10Ge

JESD

Job description

Senior FPGA Engineer £80-100k Slough Hybrid

My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities and IoT applications.

Due to the launch of a cutting-edge, and innovative project, they are looking for a Senior FPGA Engineer to join their DSP department.

Main duties:

1. Full development cycle involvement, from design to testing
2. Cross functional collaboration with a multi-disciplinary team
3. Technical liaison, and maintenance and design specification of documentation

Skills and Experience Required:

1. Deep understanding of FPGA fundamentals, fabric, and clocking resources
2. Proficiency in Verilog/System Verilog
3. Experience with RTL-level design
4. Previous telecommunications experience
5. Knowledge of 4G or 5G standards

Bonus:

1. Experience with scripting languages (e.g., Python, Shell, Perl)
2. Experience with high-speed interfaces (PCIe, 10Ge, JESD)

What you will get:

1. £80-100k
2. Healthcare & pension scheme
3. 25 days holiday + bank holidays

If you feel you have the right skills and experience for this role, please apply with an updated CV.