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Apple is seeking an ambitious Design Verification Engineer to enable bug-free silicon for mixed-signal designs within their PMU Hardware Tech team. This entry-level role focuses on pre-silicon verification, including planning and building verification environments. Candidates should possess a relevant engineering degree and have a solid understanding of digital logic, verification methodologies, and simulation processes.
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game?We have an opportunity for an ambitious and outstandingly talented Design Verification Engineer. As a member of our dynamic group, you will have the unique and exciting opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day!Apple’s PMU Hardware Tech team are responsible for delivering the power in a highly configurable and controlled way to the high end Apple SoCs, which power everything from Apple Watch, AirPods, and Apple TV to iPhone, iPad, Mac and Vision Pro.
We are looking for a recent Graduate or Junior Design Verification Engineer who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers.The responsibilities include all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.In this role you will develop verification plans in coordination with design leads and architects. You'll be responsible for planning, building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Create functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure an efficient verification flow.