Digital Verification Engineer, Crypto & Security

NXP Semiconductors NV; Glasgow; On-site; GBP 45,000 - 75,000; Full time

Job summary

NXP Semiconductors UK is expanding its Crypto & Security Competence Centre and seeks Digital Verification Engineers to help define and verify next-generation security technologies across PQC IP, secure SoC subsystems, and high-assurance cryptographic accelerators.

You will work with AI-driven verification, develop verification plans, and own complex projects from concept to silicon, applying SystemVerilog, UVM, and formal methods in a collaborative environment.

Qualifications

• Experience with SystemVerilog for testbench development and verification is required or strongly preferred.
• Experience with UVM and constrained random verification methodologies is expected.

Responsibilities

• Verify digital hardware architectures across projects.
• Create, review, and maintain verification plans and track progress.
• Specify and develop verification strategies, tests, and environments for security features and hardware co-processors.
• Adopt emerging verification methodologies and integrate them into existing flows.

Skills

SystemVerilog

UVM

Constrained Random Verification

Coverage-driven verification

Assertions (SVA)

Debugging

Education

BSc./MSc. in Electronics or Electrical Engineering

Tools

Formal Verification

Job description

We Are Actively Expanding The Crypto & Security Competence Centre (CCC&S) At NXP And We Have New Opportunities In Our Team For Digital Verification Engineers Working On Next-generation Security Technologies Such As

• Post-Quantum Cryptography (PQC) IP
• Secure SoC subsystems, including next-generation roots of trust
• High-assurance cryptographic accelerators for future platforms

At CCC&S, we are also driving a significant transformation in how hardware is designed and verified by integrating AI directly into IC design and verification flows. The role is blended with traditional verification methods whilst the AI agents are being developed. The role is blended with traditional verification methods whilst the AI agents are being developed.

Driven Verification - What You'll Be Part Of

• AI-driven verification automation - reducing regression effort while maintaining full coverage
• Intelligent debug and analysis - accelerating bug discovery and root-cause identification
• Automated test and vPlan generation - improving consistency and reducing human error

We Are Also Actively Developing Advanced Capabilities Including

• AI-assisted RTL understanding and test explanation
• Conversational debug interfaces for waveform and design interaction
• AI-driven coverage closure and test prioritisation

This is not a future vision-this transformation is already underway within CCC&S workflows.

Why This Role Stands Out

• Work on cutting-edge cryptography technologies critical to future cybersecurity
• Help define how AI transforms verification workflows and methodologies
• Join a growing organisation where your input shapes tools, processes, and technical direction
• Take ownership of high-visibility, complex projects from concept to silicon

Your Responsibilities

• Verification of digital hardware architectures.
• Creating, reviewing, and maintaining verification plans, and tracking verification progress.
• Specifying and developing verification strategies, tests, and environments for security features and hardware co-processors.
• Working with emerging verification methodologies and introducing them into existing verification flows.

Your Profile

• BSc., or MSc., degree in Electronics or Electrical Engineering.
• Some experience with SystemVerilog for testbench development and verification.
• Some experience in UVM (Universal Verification Methodology), including component creation, sequences, drivers, monitors, and scoreboards.
• Solid understanding and practical use of Constrained Random Verification techniques.
• Experience with Metrics-Driven Verification, including functional coverage and verification planning.
• Ability to write SystemVerilog Assertions (SVA) for protocol and design checking.
• Demonstrated success in achieving Coverage Closure across functional and code coverage metrics.
• Experience analysing coverage results and refining test strategies to close gaps.
• Strong debugging skills across simulations and complex verification environments.
• Knowledge of Formal Verification methods would be advantageous.

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