DFT Engineer/Architect

Raspberry Pi; Cambridge; On-site; GBP 50,000 - 80,000; Full time

Job summary

A leading company in the tech sector is seeking a DFT Engineer/Architect to join their ASIC team in Cambridge. The successful candidate will work on DFT implementation and verification, contributing to innovative silicon technologies and collaborating with various teams to ensure efficient testable devices.

Qualifications

• Hands-on experience with modern DFT tools.
• Strong grounding in IC development flows.
• Good understanding of partitioning and on-chip clocking.

Responsibilities

• Involved in hands-on DFT implementation and verification.
• Responsible for design, development, and implementation of IC DFT test solutions.
• Liaising across various groups and functions.

Skills

IC development flows

DFT tools

ATPG

Simulation debug

On-chip clocking

Tools

Siemens Tessent DFT tools

Job description

Raspberry Pi is seeking an experienced DFT Engineer / Architect to join our innovative ASIC team. The role is based on site in Cambridge with an expectation that the successful candidate comes into the office on a full time basis.

The work of the whole ASIC team includes:

• Architecture, tradeoffs with software/hardware
• RTL design
• IP selection and integration
• Verification at block and system level
• FPGA platforms for software development and extended verification
• Implementation including DFT, Synthesis, Place and Route, Timing closure and Signoff checks
• Package definition and working with assembly partners
• Validation and characterisation
• Test pattern generation and ATE bringup
• Production monitoring and management

We are looking to expand the team in Cambridge with this role.

DFT Engineer/Architect

Raspberry Pi is seeking a DFT specialist to join our innovative team. You would be involved in hands-on DFT implementation and verification across a variety of current silicon technologies. You would be responsible for design, development, and implementation of IC DFT test solutions, liaising across various groups and functions. You would be involved with architecture and development of test methodologies, ensuring adequate inclusion of test structures to enable fully and efficiently testable devices, including the following:

• Hierarchical DFT (EDT flows)
• On-chip clocking structures
• ATPG compression, serialization, and multiplexing
• Guide scan insertion providing input to Synthesis scripts
• Review, assess, and correct DFT DRC warnings
• Create STA DFT mode constraints, review failing paths, create exception list for ATPG
• Simulation (behavioural and gate-level)
• RTL design of test structures
• BIST (Memory/Logic/IP)

Job requirements:

• Willingness to contribute and share activities with a wider team
• Strong grounding in IC development flows
• Hands-on current experience with modern DFT tools
• Good understanding of partitioning and on-chip clocking
• Experience in ATPG and simulation debug

The following would also be useful:

• Experience with Siemens Tessent DFT tools preferred
• Understanding of silicon technologies, finFET, and fault models
• Logic BIST implementation, full or as part of an ATPG flow
• Familiarity with test access standards, e.g. IEEE1687