DFT Architect

JR United Kingdom; Cambridge; On-site; GBP 60,000 - 100,000; Full time

Job summary

An innovative firm is seeking a skilled DFT Architect to join their dynamic ASIC team in Cambridge. This exciting opportunity involves leading advanced DFT implementation and verification across various silicon technologies. You will collaborate closely with cross-functional teams, contributing to the full IC design flow, ensuring designs are testable and efficient. With a strong emphasis on professional growth, this role offers the chance to work with cutting-edge tools and technologies in a state-of-the-art environment. If you're passionate about DFT and ready to make a significant impact, this position is perfect for you.

Qualifications

• Proven experience in IC development flows focusing on DFT.
• Hands-on expertise with modern DFT tools and techniques.

Responsibilities

• Lead DFT implementation, verification, and validation processes.
• Develop methodologies for enhanced testability of ASIC designs.

Skills

DFT Implementation

Verification and Validation

ATPG

RTL Design

Debugging Simulations

On-chip Clocking

Tools

DFT Tools

Simulation Tools

Job description

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Job Opportunity: DFT Architect – Join an Innovative ASIC Team!

Are you an experienced DFT Architect with a passion for cutting-edge technology? This is a unique opportunity to join a highly skilled ASIC team in Cambridge, known for its innovative approach and hands-on product development. As a DFT Architect, you will be part of a collaborative team working on ground-breaking projects at the forefront of ASIC and silicon design, with plenty of scope for professional growth.

Role Overview: This position offers the chance to delve deeply into advanced DFT implementation and verification across diverse silicon technologies. As a DFT Architect, you will play a crucial role in ensuring designs are testable, efficient, and ready for production. You will work closely with cross-functional teams, contributing to the full IC design flow, including RTL design, IP integration, FPGA development, package definition, and test pattern generation.

Key Responsibilities:

• Lead hands-on DFT implementation, verification, and validation.
• Develop DFT methodologies for enhanced testability and reliability of ASIC designs.
• Ensure effective use of hierarchical DFT, on-chip clocking, and ATPG compression techniques.
• Manage scan insertion and guide synthesis scripts to ensure robust test coverage.
• Create STA DFT constraints, review paths, and set up ATPG for comprehensive testing.
• Work with cutting-edge tools for simulation (behavioural and gate-level) and BIST structures.

Who We’re Looking For:

• Proven experience in IC development flows with a focus on DFT.
• Hands-on expertise with modern DFT tools and strong knowledge in partitioning and on-chip clocking.
• Demonstrable experience in ATPG and debugging simulations.
• Proficiency in RTL design and understanding of silicon technologies.

This position requires a minimum of three days per week on-site in Cambridge, enabling close collaboration with experts and access to state-of-the-art facilities.

Ready to advance your career as a DFT Architect on a team that values innovation and technical excellence? Please contact Lucy Edmondson at IC Resources to discuss further, or apply today!